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TDA10085 Arkusz danych(PDF) 6 Page - NXP Semiconductors |
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TDA10085 Arkusz danych(HTML) 6 Page - NXP Semiconductors |
6 / 16 page 2001 Aug 31 6 Philips Semiconductors Product specification Single chip DVB-S/DSS channel receiver TDA10085HT VDDI 26 supply digital core supply voltage (typically 1.8 V) VDDE 27 supply digital supply voltage (typically 3.3 V) SDA_0 28 I/OD I2C-bus bidirectional serial input/ open drain output; equivalent to SDA but with a high-impedance state programmable via the I2C-bus; a pull-up resistor must be connected between this pin and DVCC SCL_0 29 OD I2C-bus clock output; equivalent to SCL but with a high-impedance state programmable via the I2C-bus; open drain output requiring an external pull-up resistor to 5 V VAGC 30 O or OD PWM encoded output signal for AGC; the refresh frequency of AGC information is the sampling frequency divided by 2048, the maximum signal frequency on the VAGC output is 1/4 × AGC sampling clock; the VAGC output can be selected by I2C-bus to be open-drain or have 3.3 V capability (typically, output VAGC is fed to the AGC amplifier through a single RC network) CTRL3 31 I/OD control line 3 input/open drain output; this pin function is directly programmable through the I2C-bus interface and is an input by default; it requires a pull-up resistor to 3.3 or 5 V, or a pull-down resistor to GND SDA 32 I/OD I2C-bus bidirectional serial data input/output; the open-drain output requires a pull-up resistor (typically 2.2 k Ω) to be connected between SDA and 5 V for proper operation SCL 33 I I2C-bus clock input; nominally a square wave with a maximum frequency of 400 kHz generated by the system I2C-bus master; see note 1 TMS 34 I/O boundary scan mode: test mode select input/output; provides the logic levels needed to change the TAP controller from state to state serial mode enabled (ENSERI = 1): serial TS uncorrectable output; when not in serial mode, TMS must be set to VSS TCK 35 I/O boundary scan mode: test clock input/output; TCK is an independant clock used to drive the TAP controller serial mode enabled (ENSERI = 1): TCK is the serial TS clock output; when not in serial mode, TCK must be set to VSS TRST 36 I/O boundary scan mode: test reset input/output; TRST is an active-LOW reset input to the TAP controller serial mode enabled (ENSERI = 1): test reset input/output; TRST is the serial TS PSYNC output; when not in serial mode, TRST must be set to VSS FEL 37 OD front-end locked output signal that goes HIGH when demodulator, Viterbi decoder and de-interleaver are all synchronized; open-drain output requiring an external pull-up resistor to 3.3 or 5 V; can be set via the I2C-bus to be an interrupt pin VDDI 38 supply digital core supply voltage (typically 1.8 V) VSSI 39 ground digital core ground voltage; see note 2 TDI 40 I/O boundary scan mode: test data and instruction serial input serial mode enabled (ENSERI = 1): serial TS data output; must be set to VSS when not in serial mode SYMBOL PIN TYPE DESCRIPTION |
Podobny numer części - TDA10085 |
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Podobny opis - TDA10085 |
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