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SM320F2812 Arkusz danych(PDF) 11 Page - Texas Instruments |
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SM320F2812 Arkusz danych(HTML) 11 Page - Texas Instruments |
11 / 138 page Introduction 11 December 2004 − Revised September 2006 SGUS053B Table 2−2. Signal Descriptions† (Continued) NAME DESCRIPTION PU/PD§ I/O/Z‡ PIN NO. NAME DESCRIPTION PU/PD§ I/O/Z‡ 172-PIN HFG POWER SIGNALS VDD 22 VDD 36 VDD 55 VDD 73 VDD − 1.8-V or 1.9-V Core Digital Power Pins. See Section 6.2, Recommended VDD 98 1.8-V or 1.9-V Core Digital Power Pins. See Section 6.2, Recommended Operating Conditions, for voltage requirements. VDD 110 Operating Conditions, for voltage requirements. VDD 125 VDD 140 VDD 150 VSS − VSS 31 VSS 37 VSS 51 VSS 57 VSS − VSS 76 VSS 84 Core and Digital I/O Ground Pins VSS 97 Core and Digital I/O Ground Pins VSS 103 VSS 111 VSS − VSS 126 VSS 139 VSS − VSS − VDDIO 30 VDDIO 63 VDDIO 79 3.3-V I/O Digital Power Pins VDDIO − 3.3-V I/O Digital Power Pins VDDIO 112 VDDIO 142 VDD3VFL 68 3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times after power-up sequence requirements have been met. This pin is used as VDDIO in ROM parts and must be connected to 3.3 V in ROM parts as well. † Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA. ‡ I = Input, O = Output, Z = High impedance § PU = pin has internal pullup; PD = pin has internal pulldown |
Podobny numer części - SM320F2812 |
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Podobny opis - SM320F2812 |
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