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Zakładka z wyszukiwarką danych komponentów |
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93AA46A Arkusz danych(PDF) 11 Page - Microchip Technology |
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93AA46A Arkusz danych(HTML) 11 Page - Microchip Technology |
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11 / 38 page  © 2007 Microchip Technology Inc. DS21929D-page 11 93XX46X/56X/66X/76X/86X 3.4 ERASE The ERASE instruction forces all data bits of the specified address to the logical ‘1’ state. CS is brought low following the loading of the last address bit. This falling edge of the CS pin initiates the self-timed programming cycle, except on ‘93CXX’ devices where the rising edge of CLK before the last address bit initiates the write cycle. The DO pin indicates the Ready/Busy status of the device if CS is brought high after a minimum of 250 ns low (TCSL). DO at logical ‘0’ indicates that programming is still in progress. DO at logical ‘1’ indicates that the register at the specified address has been erased and the device is ready for another instruction. FIGURE 3-1: ERASE TIMING FOR 93AAXX AND 93LCXX DEVICES FIGURE 3-2: ERASE TIMING FOR 93CXX DEVICES Note: After the Erase cycle is complete, issuing a Start bit and then taking CS low will clear the Ready/Busy status from DO. CS CLK DI DO TCSL Check Status 11 1 AN AN-1 AN-2 ••• A0 TSV TCZ BUSY Ready High-Z TWC High-Z CS CLK DI DO TCSL Check Status 11 1 AN AN-1 AN-2 ••• A0 TSV TCZ Busy Ready High-Z TWC High-Z |
Podobny numer części - 93AA46A_07 |
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Podobny opis - 93AA46A_07 |
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