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DS28EA00 Arkusz danych(PDF) 3 Page - Dallas Semiconductor

Numer części DS28EA00
Szczegółowy opis  1-Wire Digital Thermometer with Sequence Detect and PIO
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Producent  DALLAS [Dallas Semiconductor]
Strona internetowa  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS28EA00 Arkusz danych(HTML) 3 Page - Dallas Semiconductor

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DS28EA00 1-Wire Digital Thermometer with Sequence Detect and PIO
3 of 29
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
IO Pin, 1-Wire Write
Standard speed
60
120
Write-0 Low Time
(Notes 2, 17)
tW0L
Overdrive speed
6
16
µs
Standard speed
5
15
Write-1 Low Time
(Notes 2, 17)
tW1L
Overdrive speed
1
2
µs
IO Pin, 1-Wire Read
Standard speed
5
15 -
δ
Read Low Time
(Notes 2, 18)
tRL
Overdrive speed
1
2 -
δ
µs
Standard speed
tRL + δ
15
Read Sample Time
(Notes 2, 18)
tMSR
Overdrive speed
tRL + δ
2
µs
PIO Pins
Input Low Voltage
VILP
(Note 2)
0.3
V
Input High Voltage
(Note 2)
VIHP
VX = max(VPUP, VDD)
Vx-1.6
V
Input Load Current
(Note 19)
ILP
Pin at GND
-1.1
µA
Output Low Voltage
(Note 11)
VOLP
At 4mA
0.4
V
Chain-on Pullup
Impedance
RCO
(Note 5)
20
40
60
k
Ω
EEPROM
Programming Current
IPROG
(Notes 5, 20)
1.5
mA
Programming Time
tPROG
(Note 21)
10
ms
At +25°C
200k
Write/Erase Cycles (En-
durance) (Notes 22, 23)
NCY
-40°C to +85°C
50k
Data Retention
(Notes 24, 25)
tDR
At +85°C (worst case)
10
years
Temperature Converter
Conversion Current
ICONV
(Notes 5, 20)
1.5
mA
12-bit resolution (1/16°C)
750
11-bit resolution (1/8°C)
375
10-bit resolution (1/4°C)
187.5
Conversion Time
(Note 26)
tCONV
9-bit resolution (1/2°C)
93.75
ms
-10°C to +85°C
-0.5
+0.5
Conversion Error
Δϑ
below -10°C (Note 5)
-0.5
+2.0
°C
Converter Drift
ϑ
D
(Note 27)
-0.2
+0.2
°C
Note 1:
Specifications at TA = -40°C are guaranteed by design only and not production-tested.
Note 2:
System requirement.
Note 3:
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The
specified value here applies to parasitically powered systems with only one device and with the minimum 1-Wire recovery
times. For more heavily loaded systems, local power or an active pullup such as that found in the DS2482-x00, DS2480B, or
DS2490 may be required. If longer tREC is used, higher RPUP values may be tolerable.
Note 4:
Value is 25pF max. with local power. Maximum value represents the internal parasite capacitance when VPUP is first applied. If
RPUP = 2.2kΩ, 2.5µs after VPUP has been applied the parasite capacitance will not affect normal communications.
Note 5:
Guaranteed by design, characterization, and/or simulation only. Not production tested.
Note 6:
VTL, VTH, and VHY are a function of the internal supply voltage, which is itself a function VDD, VPUP, RPUP, 1-Wire timing, and
capacitive loading on IO. Lower VDD, VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of VTL,
VTH, and VHY.
Note 7:
Voltage below which, during a falling edge on IO, a logic '0' is detected.
Note 8:
The voltage on IO needs to be less than or equal to VILMAX at all times the master drives the line to a logic '0'.
Note 9:
Voltage above which, during a rising edge on IO, a logic '1' is detected.
Note 10:
After VTH is crossed during a rising edge on IO, the voltage on IO has to drop by at least VHY to be detected as logic '0'.
Note 11:
The I-V characteristic is linear for voltages less than 1V.
Note 12:
Applies to a single parasitically powered DS28EA00 attached to a 1-Wire line. These values also apply to networks of multiple
DS28EA00 with local supply.
Note 13:
The earliest recognition of a negative edge is possible at tREH after VTH has been reached on the preceding rising edge.
Note 14:
Defines maximum possible bit rate. Equal to 1/(tW0L(min) + tREC(min)).
Note 15:
Interval during the negative edge on IO at the beginning of a Presence-Detect pulse between the time at which the voltage is
80% of VPUP and the time at which the voltage is 20% of VPUP.
Note 16:
Interval after tRSTL during which a bus master is guaranteed to sample a logic '0' on IO if there is a DS28EA00 present. Minimum
limit is tPDH(max) + tFPD(max); maximum limit is tPDH(min) + tPDL(min).
Note 17:
ε in Figure 14 represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL to VTH. The actual maximum
duration for the master to pull the line low is tW1Lmax + tF - ε and tW0Lmax + tF - ε respectively.


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