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FDG8842CZ Arkusz danych(PDF) 7 Page - Fairchild Semiconductor |
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FDG8842CZ Arkusz danych(HTML) 7 Page - Fairchild Semiconductor |
7 / 8 page Typical Characteristics(Q2 P-Channel) T J = 25°C unless otherwise noted Figure 19. Gate Charge Characteristics 0.0 0.4 0.8 1.2 1.6 0 1 2 3 4 5 VDD = -10V VDD = -15V Qg, GATE CHARGE(nC) VDD = -5V ID = -0.41A 0.1 1 10 1 10 100 200 f = 1MHz VGS = 0V -VDS, DRAIN TO SOURCE VOLTAGE (V) Crss Coss Ciss 25 Figure 20. Capacitance vs Drain to Source Voltage Figure 21. Forward Bias Safe Operating Area 110 0.01 0.1 1 0.3 50 3 1ms 1s DC 100ms 10ms SINGLE PULSE TJ = MAX RATED RθJA = 415oC/W TA = 25oC -VDS, DRAIN to SOURCE VOLTAGE (V) r DS( on ) LIM ITED Figure 22. Single Pulse Maximum Power Dissipation 0.001 0.01 0.1 1 10 100 1000 0.1 1 10 TA = 25OC RθJA= 415OC/W SINGLE PULSE 20 t, PULSE WIDTH (s) Figure 23. Transient Thermal Response Curve 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 0.01 0.1 1 RθJA = 415 o C/W DUTY CYCLE-DESCENDING ORDER t, RECTANGULAR PULSE DURATION (s) D = 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE PDM t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA www.fairchildsemi.com 7 ©2007 Fairchild Semiconductor Corporation FDG8842CZ Rev.B |
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