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ML145146-6P Arkusz danych(PDF) 6 Page - LANSDALE Semiconductor Inc.

Numer części ML145146-6P
Szczegółowy opis  4-Bit Data Bus Input PLL Frequency Synthesizer
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Producent  LANSDALE [LANSDALE Semiconductor Inc.]
Strona internetowa  http://www.lansdale.com
Logo LANSDALE - LANSDALE Semiconductor Inc.

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LANSDALE Semiconductor, Inc.
ML145146
www.lansdale.com
Page 6 of 12
Issue 0
PIN DESCRIPTIONS
INPUT PINS
D0 - D3
Data Inputs (Pins 2, 1, 20, 19)
Information at these inputs is transferred to the internal
latches when the ST input is in the high state. D3 (Pin 19) is
the most significant bit.
fin
Frequency Input (Pin 3)
Input to ÷N portion of synthesizer fin is typically derived
from loop VCO and is AC coupled into Pin 3. For larger
amplitude signals (standard CMOS – logic levels) DC coupling
may be used.
OSCin/OSCout
Reference Oscillator Input/Output (Pins 7 and 8)
These pins form an on–chip reference oscillator when con-
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be con-
nected from OSCin to ground and OSCout to ground. OSCin
may also serve as input for an externally–generated reference
signal. This signal is typically AC coupled to OSCin, but for
larger amplitude signals (standard CMOS–logic levels) DC
coupling may also be used. In the external reference mode, no
connection is required to OSCout.
A0 - A2
Address Inputs (Pins 9, 10, 11)
A0, A1 and A2 are used to define which latch receives the
information on the data input lines. The addresses refer to the
following latches.
ST
Strobe Transfer (Pin 12)
The rising edge of strobe transfers data into the addressed
latch. The falling edge of strobe latches data into the latch.
This pin should normally be held low to avoid loading latches
with invalid data.
OUTPUT PINS
PDout
Single–ended Phase Detector Output (Pin 5)
Three–state output of phase detector for use as loop error
signal.
Frequency fV>fR or fV Leading: Negative Pulses
Frequency fV<fR or fV Lagging: Negative Pulses
Frequency fV=fR and Phase Coincidence: High–Impedance
State
LD
Lock Detector (Pin 13)
High level when loop is locked (fR, fV of same phase and
frequency). Pulses low when loop is out of lock.
MC
Modulus Control (Pin 14)
Signal generated by the on–chip control logic circuitry for
controlling an external dual–modulus prescaler. The modulus
control level is low at beginning of a count cycle and remains
low until the ÷A counter has counted down from its pro-
grammed value. At this time, modulus control goes high and
remains high until the ÷N counter has counted the rest of the
way down from its programmed value (N – A additional count-
er since both ÷N and ÷A are counting down during the first
portion of the cycle). Modulus control is then set back low, the
counters preset to their respective programmed values, and the
above sequence repeated. This provides for a total programma-
ble divide value (NT) = N • P ÷ A where P and P ÷ 1 represent
the dual–modulus prescaler divide values respectively for high
and low modulus control levels. N the number programmed
into the ÷N counter and A the number programmed into the
÷A counter.
fV
÷N Counter Output (Pin 15)
This pin is the output of the ÷N counter that is internallly
connected to the phase detector input. With this output avail-
able, the ÷N counter can be used independently.
φV, φR
Phase Detector Outpiuts (Pins 16 adn 17)
These phase detector outputs can be combined externally for
a loop error signal. A single–ended output is also available for
this purpose (see PDout).
If frequency fV is greater than fR or if the phase of fV is
leading, then error information is provided by
φV pulsing low
φR remains essentially high.
If the frequency fV is less than fR or if the phase of fV is
lagging, then error information is provided by
φR pulsing low
φV remains essentially high.
If the frequency of fV = fR and both are in phase, then both
φV and φR remain high except for a small minimum time peri-
od when both pulse low in phase.
fR
÷R Counter Output (Pin 18)
This is the output of the ÷ R counter that is internally con-
nected to the phase detector input. With this output available,
the ÷ R counter can be used independently.
POWER SUPPLY PINS
VSS
Ground (Pin 4)
Circuit Ground
VDD
Positive Power Supply (Pin 6)
The positive supply voltage may range from 3.0 to 9.0 V
with respect to VSS.
A2
A1
A0
D0
D1
D2
D3
Selected
Function
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Latch 0
Latch 1
Latch 2
Latch 3
Latch 4
Latch 5
Latch 6
Latch 7
÷ A Bits
÷ A Bits
÷ N Bits
÷ N Bits
÷ N Bits
Reference Bits
Reference Bits
Reference Bits
0
4
0
4
8
0
4
8
1
5
1
5
9
1
5
9
2
6
2
5
2
6
10
3
3
7
3
7
11


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