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CD2481 Arkusz danych(PDF) 4 Page - Intel Corporation |
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CD2481 Arkusz danych(HTML) 4 Page - Intel Corporation |
4 / 222 page CD2481 — Programmable Four-Channel Communications Controller 4 Datasheet 5.4 DMA Operation ................................................................................................... 45 5.4.1 Bus Acquisition Cycle............................................................................. 46 5.4.2 DMA Data Transfer ................................................................................ 46 5.4.3 Bus Error Handling ................................................................................. 47 5.4.4 A and B Buffers and Chaining ................................................................ 48 5.4.5 Transmit DMA Transfer .......................................................................... 49 5.4.6 Synchronous Transmitter Examples ...................................................... 50 5.4.7 Receive DMA Transfer ........................................................................... 52 5.5 Bit Rate Generation and Data Encoding ............................................................. 60 5.6 Hardware Configurations .................................................................................... 67 5.6.1 Interface to a 32-Bit Data Bus ................................................................ 68 5.6.2 DMA Connections for the CD2481 ......................................................... 68 5.6.3 Recommended CD2481 as a DTE and DCE Interface .......................... 68 6.0 Microcode Download.............................................................................................. 70 6.1 Microcode Download Information........................................................................ 70 6.1.1 Registers Specific to Download Operations ........................................... 70 6.1.2 Download Code Example....................................................................... 71 7.0 Protocol Processing ............................................................................................... 75 7.1 HDLC Processing................................................................................................ 75 7.1.1 FCS (Frame Check Sequence) .............................................................. 75 7.1.2 HDLC Transmit Mode............................................................................. 75 7.1.3 HDLC Receive Mode ............................................................................. 76 7.2 PPP (Point-to-Point Protocol) Mode.................................................................... 77 7.2.1 Character Format ................................................................................... 77 7.2.2 Frame Format ........................................................................................ 77 7.2.3 FCS (Frame Check Sequence) .............................................................. 77 7.2.4 Transparency ......................................................................................... 78 7.2.5 Definition of a Valid Frame ..................................................................... 79 7.2.6 Transmitter ............................................................................................. 79 7.2.7 Receiver ................................................................................................. 80 7.3 SLIP Processing.................................................................................................. 81 7.3.1 Framing .................................................................................................. 81 7.3.2 Debugging Aids ...................................................................................... 82 7.4 MNP4‚/ARAP Protocol Processing...................................................................... 82 7.4.1 Framing .................................................................................................. 82 7.4.2 MNP4‚/ARAP FCS (Frame Check Sequence) Calculation..................... 83 7.5 Async Processing................................................................................................ 83 7.5.1 Transmitter In-Band Flow Control .......................................................... 83 7.5.2 Receiver In-Band Flow Control .............................................................. 84 7.5.3 Out-of-Band Flow Control ...................................................................... 85 7.5.4 Line Break Detection and Generation .................................................... 86 7.5.5 Special Character Transmission ............................................................ 86 7.5.6 Special Character Recognition............................................................... 87 7.5.7 Special Character Range ....................................................................... 87 7.5.8 UNIX Support Features .......................................................................... 88 7.6 Bisync Protocol ................................................................................................... 92 7.6.1 Bisync Transmit Processing ................................................................... 92 7.6.2 Bisync Receive Processing .................................................................... 92 |
Podobny numer części - CD2481 |
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Podobny opis - CD2481 |
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