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74LV32PW Arkusz danych(PDF) 4 Page - NXP Semiconductors |
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74LV32PW Arkusz danych(HTML) 4 Page - NXP Semiconductors |
4 / 15 page 74LV32_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 November 2007 4 of 15 NXP Semiconductors 74LV32 Quad 2-input OR gate [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] Ptot derates linearly with 12 mW/K above 70 °C. [3] Ptot derates linearly with 8 mW/K above 70 °C. [4] Ptot derates linearly with 5.5 mW/K above 60 °C. [5] Ptot derates linearly with 4.5 mW/K above 60 °C. 8. Recommended operating conditions [1] The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to VCC = 1.0 V (with input levels GND or VCC). Ptot total power dissipation Tamb = −40 °C to +125 °C DIP14 package [2] - 750 mW SO14 package [3] - 500 mW (T)SSOP14 package [4] - 500 mW DHVQFN14 package [5] - 500 mW Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VCC supply voltage[1] 1.0 3.3 5.5 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature −40 +25 +125 °C ∆t/∆V input transition rise and fall rate VCC = 1.0 V to 2.0 V - - 500 ns/V VCC = 2.0 V to 2.7 V - - 200 ns/V VCC = 2.7 V to 3.6 V - - 100 ns/V VCC = 3.6 V to 5.5 V - - 50 ns/V |
Podobny numer części - 74LV32PW |
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Podobny opis - 74LV32PW |
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