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74LV138PW Arkusz danych(PDF) 3 Page - NXP Semiconductors |
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74LV138PW Arkusz danych(HTML) 3 Page - NXP Semiconductors |
3 / 17 page 74LV138_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 November 2007 3 of 17 NXP Semiconductors 74LV138 3-to-8 line decoder/demultiplexer; inverting 5. Pinning information 5.1 Pinning Fig 3. Functional diagram mna372 ENABLE EXITING Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 7 9 10 11 12 13 14 15 A0 A1 A2 3-to-8 DECODER 3 2 1 6 5 4 E2 E1 E3 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration DIP16, SO16 and (T)SSOP16 Fig 5. Pin configuration DHVQFN16 138 A0 VCC A1 Y0 A2 Y1 E1 Y2 E2 Y3 E3 Y4 Y7 Y5 GND Y6 001aad033 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 001aah106 74LV138 Y7 Y5 E3 Y4 E2 Y3 E1 Y2 A2 Y1 A1 Y0 Transparent top view 7 10 6 11 5 12 4 13 3 14 2 15 terminal 1 index area VCC(1) |
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