SM5921A

SEIKO NPC CORPORATION —1

8-channel Lip Sync Delay

OVERVIEW

The SM5921A is an SDRAM controller LSI for audio applications. It stores 64-fs slot 3-wire serial format

audio data input at sampling frequency fs in SDRAM, and can access data at an arbitrary address to add a delay

to each channel data. It also has a direct mute function to mute the audio data.

FEATURES

Functions

I

System clock input

64fs (fs = 32 to 192kHz) bit clock

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Sampling frequency: fs = 32 to 192kHz support

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Data input/output

3-wire serial, 8-channel PCM

64 clock/slot, word clock polarity inversion

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Direct mute function

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MCU interface: 3-wire serial

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Delay settings: sum of intrinsic delay and individ-

ual delay

• Intrinsic delay (common to all channels,

default = 0 samples, 16-sample units)

• Individual delay (independent for each channel,

default = 0 samples, 1-sample units)

Maximum delay values

1365.3ms @ fs = 48kHz

682.7ms @ fs = 96kHz

341.3ms @ fs = 192kHz

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Address shift function:

×1, ×2, ×4 support

Delay time can be multiplied between

×1, ×2, or

×4 times without changing the delay set value.

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SDRAM interface: 16M/64M/128M (

×16 devices

supported)

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Package: 64-pin QFP

Structure

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Silicon-gate CMOS

Applications

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Audio delay for multi-channel PCM signals

ORDERING INFORMATION

PINOUT

(Top view)

PACKAGE DIMENSIONS

(Unit: mm)

Weight: 0.35g

Note. Dimensions without tolerance are reference values.

Device

Package

SM5921AF

64-pin QFP

21

22

23

24

25

26

27

28

29

30

31

32

49

50

51

52

53

54

55

56

57

58

59

60

DOC

DOD

A4

A5

A6

A7

A8

A9

CKE

CLKO

DQM

VSS

VDD

DQ3

DQ2

DQ1

DQ0

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

17

VDD

61

DQ8

64

VSS

62

WPOLN

63

OEN

18

TEST

19

DOA

20

DOB

12 ± 0.4

10 ± 0.1

0.5

0.18

− 0.05

+ 0.09

S

0.08

S

0 to 10

0.125 − 0.025

+ 0.075