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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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ST62T80B Arkusz danych(PDF) 48 Page - STMicroelectronics |
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ST62T80B Arkusz danych(HTML) 48 Page - STMicroelectronics |
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48 / 80 page  48/80 ST62T80B/E80B AUTO-RELOAD TIMER (Cont’d) AR Status Control Register 1(ARSC1) Address: E7h — Read/Write Bist 7-5 = PS2-PS0: Prescaler Division Selection Bits 2-0. These bits determine the Prescaler divi- sion ratio. The prescaler itself is not affected by these bits. The prescaler division ratio is listed in the following table: Table 16. Prescaler Division Ratio Selection Bit 4 = D4: Reserved. Must be kept reset. Bit 3-2 = SL1-SL0: Timer Input Edge Control Bits 1- 0. These bits control the edge function of the Timer input pin for external synchronization. If bit SL0 is re- set, edge detection is disabled; if set edge detection is enabled. If bit SL1 is reset, the AR Timer input pin is rising edge sensitive; if set, it is falling edge sen- sitive. Bit 1-0 = CC1-CC0: Clock Source Select Bit 1-0. These bits select the clock source for the AR Timer through the AR Multiplexer. The programming of the clock sources is explained in the following Table 17: Table 17. Clock Source Selection. AR Load Register ARLR. The ARLR load register is used to read or write the ARTC counter register “on the fly” (while it is counting). The ARLR regis- ter is not affected by system reset. AR Load Register (ARLR) Address: EBh — Read/Write Bit 7-0 = D7-D0: Load Register Data Bits. These are the load register data bits. AR Reload/Capture Register. The ARRC re- load/capture register is used to hold the auto-re- load value which is automatically loaded into the counter when overflow occurs. AR Reload/Capture (ARRC) Address: E9h — Read/Write Bit 7-0 = D7-D0: Reload/Capture Data Bits. These are the Reload/Capture register data bits. AR Compare Register. The CP compare register is used to hold the compare value for the compare function. AR Compare Register (ARCP) Address: EAh — Read/Write Bit 7-0 = D7-D0: Compare Data Bits. These are the Compare register data bits. 70 PS2 PS1 PS0 D4 SL1 SL0 CC1 CC0 PS2 PS1 PS0 ARPSC Division Ratio 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 2 4 8 16 32 64 128 SL1 SL0 Edge Detection X 0 Disabled 0 1 Rising Edge 1 1 Falling Edge CC1 CC0 Clock Source 00 Fint 01 Fint Divided by 3 1 0 ARTIMin Input Clock 11 Reserved 70 D7 D6 D5 D4 D3 D2 D1 D0 70 D7 D6 D5 D4 D3 D2 D1 D0 70 D7 D6 D5 D4 D3 D2 D1 D0 48 |
Podobny numer części - ST62T80B_07 |
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Podobny opis - ST62T80B_07 |
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