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TMPR4956C Arkusz danych(PDF) 8 Page - Toshiba Semiconductor |
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TMPR4956C Arkusz danych(HTML) 8 Page - Toshiba Semiconductor |
8 / 286 page Table of Contents iv 8.21.2 Exception Types.................................................................................................................... 8-25 8.21.3 Exception Trap Processing .................................................................................................... 8-26 8.21.4 Flags ..................................................................................................................................... 8-26 8.21.5 FPU Exceptions .................................................................................................................... 8-27 8.21.6 Saving and Restoring State .................................................................................................... 8-30 8.21.7 Trap Handlers for IEEE Standard 754 Exceptions ................................................................. 8-30 9. Initialization Interface ....................................................................................................................... 9-1 9.1 Functional Overview ..................................................................................................................... 9-1 9.1.1 System Coordination............................................................................................................... 9-1 9.2 Reset Signal Description ................................................................................................................ 9-2 9.2.1 Power-On Reset....................................................................................................................... 9-2 9.2.2 Cold Reset............................................................................................................................... 9-3 9.2.3 Soft Reset ................................................................................................................................ 9-4 9.3 User-Selectable Mode Configurations ............................................................................................ 9-5 9.3.1 System Bus Interface Modes.................................................................................................... 9-5 9.3.2 Clock Divisor for the System Bus ............................................................................................ 9-5 9.3.3 System Endianness.................................................................................................................. 9-5 9.3.4 Enabling and Disabling the Timer Interrupt ............................................................................ 9-5 9.3.5 System Bus Width Setting ....................................................................................................... 9-5 10. Clock Interface ................................................................................................................................ 10-1 10.1 Signal Terminology...................................................................................................................... 10-1 10.2 Basic System Clocks .................................................................................................................... 10-2 10.2.1 MasterClock.......................................................................................................................... 10-2 10.2.2 CPUCLK.............................................................................................................................. 10-2 10.2.3 GBUSCLK ........................................................................................................................... 10-2 10.2.4 CPUCLK-to-GBUSCLK Division......................................................................................... 10-3 10.2.5 Phase-Locked Loop (PLL) .................................................................................................... 10-3 10.3 Connecting Clocks to a Phase-Locked System.............................................................................. 10-4 11. TX4956 System Interface................................................................................................................. 11-1 11.1 Introduction................................................................................................................................. 11-1 11.2 Explanation of System Interface of R5000 Type Protocol Mode .................................................. 11-1 11.2.1 Interface Bus ......................................................................................................................... 11-2 11.2.2 Address Cycle and Data Cycle............................................................................................... 11-2 11.2.3 Issue Cycle ............................................................................................................................ 11-3 11.2.4 Handshake Signal.................................................................................................................. 11-4 11.2.5 System Interface Protocol of R5000 Type.............................................................................. 11-4 11.2.6 Processor Requests and External Requests............................................................................. 11-6 11.2.7 Handling of Requests .......................................................................................................... 11-10 11.2.8 Processor Request and External Request Protocol ............................................................... 11-12 11.2.9 Data Transfer ...................................................................................................................... 11-25 11.2.10 System Interface Cycle Time ............................................................................................... 11-26 11.2.11 System Interface Command and Data Identifiers................................................................. 11-27 11.2.12 System Interface Addresses ................................................................................................. 11-32 11.2.13 Mode Register of System Interface (G2SConfig).................................................................. 11-32 11.2.14 Data Error Detection........................................................................................................... 11-33 11.3 System Interface of R4300 Type Protocol Mode ........................................................................ 11-34 11.3.1 System Interface Description of R4300 Type Protocol Mode ............................................... 11-34 11.3.2 System Events ..................................................................................................................... 11-38 11.3.3 System Event Sequences and the SysAD Bus Protocol......................................................... 11-38 11.3.4 System Interface Protocols .................................................................................................. 11-41 11.3.5 Timing Summary ................................................................................................................ 11-43 11.3.6 Arbitration .......................................................................................................................... 11-47 11.3.7 Issuing Commands.............................................................................................................. 11-48 11.3.8 Processor Write Request...................................................................................................... 11-48 11.3.9 Processor Read Request....................................................................................................... 11-50 11.3.10 External Write Request ....................................................................................................... 11-50 11.3.11 External Read Response ...................................................................................................... 11-52 11.3.12 Flow Control....................................................................................................................... 11-54 |
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