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TLP750 Arkusz danych(PDF) 4 Page - Toshiba Semiconductor |
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TLP750 Arkusz danych(HTML) 4 Page - Toshiba Semiconductor |
4 / 7 page TLP750 2007-10-01 4 (Note 8) CML is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the logic low state(VO < 0.8V). CMH is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic high state(VO > 2.0V). (Note 9) Maximum electrostatic discharge voltage for any pins: 100V(C=200pF, R=0) Test Circuit 1: Switching Time Test Circuit 1 8 7 6 5 3 4 2 RL VO Pulse Input PW=100μs Duty ratio=1/10 IF Monitor VCC=5V Output Monitor 1.5V 5V 1.5V VO IF 0 tpHL tpLH VOL IF Test Circuit 2: Common Mode Noise Immunity Test Circuit IF VCC=5V RL VO Pulse generator VCM ZO=50Ω VCM VO (IF=0mA) VOL 0.8V 2V 5V 0V 200V 90% 10% tf tr VO (IF=16mA) Output Monitor 1 8 7 6 5 3 4 2 ) ( ) ( = ) ( ) ( = μs f t V 160 L CM , μs r t V 160 H CM |
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