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SN74AHC04DRE4 Arkusz danych(PDF) 3 Page - Texas Instruments |
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SN74AHC04DRE4 Arkusz danych(HTML) 3 Page - Texas Instruments |
3 / 13 page www.ti.com See Note A See Note A See Note B B1–B8 Y9–Y13 PERI LOGIC OUT C14–C17 HOST LOGIC IN VCC CABLE DIR HD A1–A8 A9–A13 PERI LOGIC IN A14–A17 HOST LOGIC OUT 42 48 1 19 24 30 25 NOTES: A. The PMOS transistors prevent backdriving current from the signal pins to VCC CABLE when VCC CABLE is open or at GND. The PMOS transistor is turned off when the associated driver is in the low state. B. The PMOS transistor prevents backdriving current from the signal pins to VCC CABLE when VCC CABLE is open or at GND. C. Active input detection circuit forces Y9–Y13 to the high state after power on, until one of the A9–A13 pins goes high (see below). See Note C Power-On Reset Q R D C Timer OUT A13 A12 A11 A10 A9 Active Input Detection Circuit SN74LVCZ161284A 19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP SCES358B – SEPTEMBER 2001 – REVISED MAY 2005 LOGIC DIAGRAM 3 |
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