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74LV259D Arkusz danych(PDF) 10 Page - NXP Semiconductors

Numer części 74LV259D
Szczegółowy opis  8-bit addressable latch
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74LV259D Arkusz danych(HTML) 10 Page - NXP Semiconductors

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74LV259_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 2 January 2008
10 of 19
NXP Semiconductors
74LV259
8-bit addressable latch
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9.
The conditional reset input (MR) to output (Qn) propagation delays
001aah124
MR input
Qn output
tPHL
tW
VM
VOH
VCC
GND
VOL
VM
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 10. The data set-up and hold times for the D input to the LE input
001aah125
GND
GND
th
tsu
th
tsu
VM
VM
VM
VCC
VOH
VOL
VCC
Qn output
Q = D
Q = D
LE input
D input
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 11. The address input set-up and hold times for the An inputs to the LE input
001aah126
VM
ADDRESS STABLE
VM
th
tsu
VCC
GND
VCC
GND
LE input
An input


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