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74LV259DB Arkusz danych(PDF) 3 Page - NXP Semiconductors |
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74LV259DB Arkusz danych(HTML) 3 Page - NXP Semiconductors |
3 / 19 page 74LV259_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 2 January 2008 3 of 19 NXP Semiconductors 74LV259 8-bit addressable latch 5. Pinning information 5.1 Pinning 5.2 Pin description Fig 3. Functional diagram 001aah120 1 OF 8 DECODER 8 LATCHES A0 1 A1 2 A2 3 LE 14 MR 15 D 13 Q0 4 Q1 5 Q2 6 Q3 7 Q4 9 Q5 10 Q6 11 Q7 12 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration DIP16, SO16 and (T)SSOP16 Fig 5. Pin configuration DHVQFN16 74LV259 A0 VCC A1 MR A2 LE Q0 D Q1 Q7 Q2 Q6 Q3 Q5 GND Q4 001aah127 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 001aah117 74LV259 Q3 Q5 Q2 Q6 Q1 VCC(1) Q7 Q0 D A2 LE A1 MR Transparent top view 7 10 6 11 5 12 4 13 3 14 2 15 terminal 1 index area Table 2. Pin description Symbol Pin Description A0 1 address input A1 2 address input A2 3 address input GND 8 ground (0 V) Q[0:7] 4, 5, 6, 7, 9, 10, 11, 12 latch output |
Podobny numer części - 74LV259DB |
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Podobny opis - 74LV259DB |
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