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74LV259BQ Arkusz danych(PDF) 7 Page - NXP Semiconductors

Numer części 74LV259BQ
Szczegółowy opis  8-bit addressable latch
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74LV259BQ Arkusz danych(HTML) 7 Page - NXP Semiconductors

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74LV259_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 2 January 2008
7 of 19
NXP Semiconductors
74LV259
8-bit addressable latch
10. Dynamic characteristics
Table 8.
Dynamic characteristics
GND = 0 V; For test circuit see Figure 12.
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
tpd
propagation delay D to Qn; see Figure 8
[2]
VCC = 1.2 V
-
105
-
-
-
ns
VCC = 2.0 V
-
36
49
-
61
ns
VCC = 2.7 V
-
26
36
-
45
ns
VCC = 3.0 V to 3.6 V; CL =15pF
[3]
-17-
-
-
ns
VCC = 3.0 V to 3.6 V
[3]
-
20
29
-
36
ns
tpd
propagation delay An to Qn; see Figure 7
[2]
VCC = 1.2 V
-
105
-
-
-
ns
VCC = 2.0 V
-
36
49
-
61
ns
VCC = 2.7 V
-
26
36
-
45
ns
VCC = 3.0 V to 3.6 V; CL =15pF
[3]
-17-
-
-
ns
VCC = 3.0 V to 3.6 V
[3]
-
20
29
-
36
ns
tpd
propagation delay LE to Qn; Figure 6
[2]
VCC = 1.2 V
-
100
-
-
-
ns
VCC = 2.0 V
-
34
48
-
60
ns
VCC = 2.7 V
-
25
35
-
44
ns
VCC = 3.0 V to 3.6 V; CL =15pF
[3]
-16-
-
-
ns
VCC = 3.0 V to 3.6 V
[3]
-
19
28
-
35
ns
tPHL
HIGH to LOW
propagation delay
MR to Qn; Figure 9
VCC = 1.2 V
-
90
-
-
-
ns
VCC = 2.0 V
-
31
43
-
53
ns
VCC = 2.7 V
-
23
31
-
39
ns
VCC = 3.0 V to 3.6 V; CL =15pF
[3]
-14-
-
-
ns
VCC = 3.0 V to 3.6 V
[3]
-
17
25
-
31
ns
tW
pulse width
LE, HIGH or LOW; see Figure 6
VCC = 2.0 V
34
10
-
41
-
ns
VCC = 2.7 V
25
8
-
30
-
ns
VCC = 3.0 V to 3.6 V
[3]
20
6
-
24
-
ns
tW
pulse width
MR, LOW; see Figure 9
VCC = 2.0 V
34
10
-
41
-
ns
VCC = 2.7 V
25
8
-
30
-
ns
VCC = 3.0 V to 3.6 V
[3]
20
6
-
24
-
ns


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