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74LV259BQ Arkusz danych(PDF) 8 Page - NXP Semiconductors

Numer części 74LV259BQ
Szczegółowy opis  8-bit addressable latch
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74LV259BQ Arkusz danych(HTML) 8 Page - NXP Semiconductors

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74LV259_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 2 January 2008
8 of 19
NXP Semiconductors
74LV259
8-bit addressable latch
[1]
Typical values are measured at Tamb =25 °C.
[2]
tpd is the same as tPLH and tPHL.
[3]
Typical value measured at VCC = 3.3 V.
[4]
CPD is used to determine the dynamic power dissipation (PD in µW).
PD =CPD × VCC2 × fi × N+ ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(C
L × VCC
2
× f
o) = sum of outputs.
tsu
set-up time
D, An to LE; see Figure 10 and
Figure 11
VCC = 1.2 V
-
35
-
-
-
ns
VCC = 2.0 V
24
12
-
29
-
ns
VCC = 2.7 V
18
9
-
21
-
ns
VCC = 3.0 V to 3.6 V
[3]
14
7
-
17
-
ns
th
hold time
D to LE; see Figure 10
VCC = 1.2 V
-
−30
-
-
-
ns
VCC = 2.0 V
5
−10
-
5
-
ns
VCC = 2.7 V
5
−8-
5
-
ns
VCC = 3.0 V to 3.6 V
[3]
5
−6-
5
-
ns
th
hold time
An to LE; see Figure 11
VCC = 1.2 V
-
−20
-
-
-
ns
VCC = 2.0 V
5
−7-
5
-
ns
VCC = 2.7 V
5
−5-
5
-
ns
VCC = 3.0 V to 3.6 V
[3]
5
−4-
5
-
ns
CPD
power dissipation
capacitance
CL = 50 pF; fi = 1 MHz;
VI = GND to VCC
[4]
19
pF
Table 8.
Dynamic characteristics …continued
GND = 0 V; For test circuit see Figure 12.
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max


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