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AD5544ARS Arkusz danych(PDF) 7 Page - Analog Devices

Numer części AD5544ARS
Szczegółowy opis  Quad, Current-Output, Serial-Input 16-/14-Bit DACs
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Strona internetowa  http://www.analog.com
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AD5544ARS Arkusz danych(HTML) 7 Page - Analog Devices

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AD5544/AD5554
Rev. A | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
28
27
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24
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17
16
15
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4
5
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13
14

AD5544/
AD5554
TOP VIEW
(Not to Scale)
AGNDA
AGNDD
IOUTA
IOUTD
VREFA
VREFD
RFBARFBD
MSB
DGND
VSS
VDD
AGNDF
CLK
SDO
SDI
NC
RFBB
RFBC
VREFB
VREFC
IOUTB
IOUTC
AGNDBAGNDC
NC = NO CONNECT
LDAC
CS
RS
Figure 3. AD5544/AD5554 Pin Configuration
Table 4. Pin Function Descriptions
Pin
No.
Name
Function
1
AGNDA
DAC A Analog Ground.
2
IOUTA
DAC A Current Output.
3
VREFA
DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. Pin can be tied to VDD pin.
4
RFBA
Establish voltage output for DAC A by connecting to external amplifier output.
5
MSB
MSB Bit. Set pin during a reset pulse (RS) or at system power ON if tied to ground or VDD.
6
RS
Reset Pin, Active Low Input. Input registers and DAC registers are set to all zeros or half-scale code (8000H for AD5544
and 2000H for AD5554) determined by the voltage on the MSB pin. Register Data = 0000H when MSB = 0.
Register Data = 8000H for AD5544 and 2000H.
7
VDD
Positive Power Supply Input. Specified range of operation 5 V ±10%.
8
CS
Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register data to the input
register when CS/LDAC returns high. Does not effect LDAC operation.
9
CLK
Clock Input. Positive edge clocks data into shift register.
10
SDI
Serial Data Input. Input data loads directly into the shift register.
11
RFBB
Establish voltage output for DAC B by connecting to external amplifier output.
12
VREFB
DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. Pin can be tied to VDD pin.
13
IOUTB
DAC B Current Output.
14
AGNDB
DAC B Analog Ground.
15
AGNDC
DAC C Analog Ground.
16
IOUTC
DAC C Current Output.
17
VREFC
DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. Pin can be tied to VDD pin.
18
RFBC
Establish voltage output for DAC C by connecting to external amplifier output.
19
NC
No Connect. Leave pin unconnected.
20
SDO
Serial Data Output. Input data loads directly into the shift register. Data appears at SDO, 19 clock pulses for AD5544
and 17 clock pulses for AD5554 after input at the SDI pin.
21
LDAC
Load DAC Register Strobe, Level Sensitive Active Low. Transfers all input register data to DAC registers. Asynchronous
active low input. See Table 5 and Table 6 for operation.
22
AGNDF
High Current Analog Force Ground.
23
VSS
Negative Bias Power Supply Input. Specified range of operation: −5.5 V to +0.3 V.
24
DGND
Digital Ground Pin.
25
RFBD
Establish Voltage Output for DAC D by Connecting to External Amplifier Output.
26
VREFD
DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. Pin can be tied to VDD pin.
27
IOUTD
DAC D Current Output.
28
AGNDD
DAC D Analog Ground.


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