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ST486 Arkusz danych(PDF) 10 Page - STMicroelectronics |
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ST486 Arkusz danych(HTML) 10 Page - STMicroelectronics |
10 / 34 page 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SELECTOR or SEGMENT +8 BASE 31 - 24 G D 0 AVL LIMIT 19 - 16 +6 P DPL DT TYPE BASE 23 - 16 +4 BASE 15 - 0 +2 LIMIT 15 - 0 +0 Table 2 - 5. Register and Descriptor Save Format Instruction Opcode Parameters Core Clocks RSDC 0F 79 [mod sreg3 r/m] sreg3, mem80 10 ST486DX - SMM IMPLEMENTATION 18 2.3 SMM Instruction Summary SGS-Thomson has added seven new instructions to the X86 standard instruction set to aid in SMM programming. These instructions are only valid when: CPL = 0 and SMI is enabled (CCR1 bit 1 = 1) and SMAR size > 0 and either [in SMM mode or SMAC is on (CCR1 bit 2 =1)] The CPU will generate an undefined opcode fault when the above conditions are not met and one of the SMM instructions are executed. The assembly language macro SMIMAC.INC listed in Ap- pendix A will automatically generate the appropriate machine code when included in a source file containing SGS-Thomson SMM instructions. Most of the SGS-Thomson SMM instructions are used to access the non-programmer visible inter- nal descriptors. The standard x86 instructions can not access this information inside the CPU. This information is stored in memory in a 10 Byte area that is comprised of both the descriptor (8-Bytes) and the segment register/selector (2 Bytes). The 8 Byte descriptor is in the same format that is found in the GDT or LDT. If the data area is dword aligned, it will minimize the memory access time. 2.3.1 RSDC - Restore Register and Descriptor RSDC loads the information at the mem80 into a segment register/selector and its associated de- scriptor. Attempting to use this instruction to load the Code Segment or Code Selector will gener- ate an invalid opcode instruction. Code Segment or Code Selector is restored from the SMM header as part of the RSM instruction. |
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