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ST5088FN Arkusz danych(PDF) 7 Page - STMicroelectronics |
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ST5088FN Arkusz danych(HTML) 7 Page - STMicroelectronics |
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7 / 33 page  amplifier which provides from 0 to 15 dB of addi- tional gain in 1 dB step. The total transmit gain should be adjusted so that, at reference point A, see Block Diagram description, the internal 0 dBmO voltage is 0.739 V (overload level is 1.06 Vrms). Second stage amplifier can be pro- grammed with bits 4 to 7 of CR5. To temporarily mute the transmit input, bit TE (6 of CR4) may be set low. In this case, the analog transmit signal is grounded and the sidetone path is also disabled. An active RC prefilter then precedes the 8th order band pass switched capacitor filter. A/D converter has a compressing characteristic according to CCITT A or mu255 coding laws, which must be selected by setting bits MA, IA in register CR0. A precision on chip voltage reference ensures accu- rate and highly stable transmission levels. Any offset voltage arising in the gain-set amplifier, the filters or the comparator is cancelled by an in- ternal autozero circuit. Each encode cycle begins immediatly at the be- ginning of the selected Transmit time slot. The to- tal signal delay referenced to the start of the time slot is approximatively 195 µs (due to the transmit filter) plus 123 µs (due to encoding delay), which totals 320 µs. Voice data is shifted out on DX dur- ing the selected time slot on the transmit rising adges of MCLK. Receive section: Voice Data is shifted into the decoder’s Receive voice data Register via the DR pin during the se- lected time slot on the 8 receive edges of MCLK. The decoder consists of an expanding DAC with either A or MU255 law decoding characteristic which is selected by the same control instruction used to select the Encode law during intitializa- tion. Following the Decoder is a 3400 Hz 6th or- der low pass switched capacitor filter with integral Sin X/X correction for the 8 kHz sample and hold. 0 dBmO voltage at this (B) reference point (see Block Diagram description) is 0.49 Vrms. A tran- scient suppressing circuitry ensure interference noise suppression at power up. The analog speech signal output can be routed either to earpiece (VFR+,VFR- outputs) or to loud- speaker (LS+, LS- outputs) by setting bits SL and SE (1 and 0 of CR4). Total signal delay is approximatively 190 µs (filter plus decoding delay) plus 62.5 µs (1/2 frame) which gives approximatively 252 µs. Differential outputs VFR+,VFR- are intended to di- rectly drive an earpiece. Preceding the outputs is a programmable attenuation amplifier, which must be set by writing to bits 4 to 7 in register CR6. At- tenuations in the range 0 to -15 dB relative to the maximum level in 1 dB step can be programmed. The input of this programmable amplifier is the summ of several signals which can be selected by writing to register CR4.: - Receive speech signal which has been de- coded and filtered, - Internally generated tone signal, (Tone ampli- tude is programmed with bits 4 to 7 of register CR7), - Sidetone signal, the amplitude of which is pro- grammed with bits 0 to 3 of register CR5 VFR+ and VFR- outputsare capable of driving output power level up to 14mW into differentially con- nected load impedance between 100 and 400 Ω. Differential outputs LS+,LS- are intended to di- rectly drive a Loudspeaker. Preceding the outputs is a programmable attenuation amplifier, which must be set by writing to bits 0 to 3 in register CR6. Attenuations in the range 0 to -30 dB rela- tive to the maximum level in 2.0 dB step can be programmed. The input of this programmable am- plifier can be the summ of signals which can be selected by writing to register CR4: - Receive speech signal which has been de- coded and filtered, - Internally generated tone signal, (Tone ampli- tude is programmed with bits 4 to 7 of register CR7), - EAIN input which may be an alternate Ring signal or any voice frequency band limited signal. (An external decoupling capacitor of about 0.1 µF is necessary). Receive voice signal may be directed to output HFO by means of bit HFE in Register CR4. After processing, signal must be re-entered through in- put HFI to Loudspeaker amplifier input. (An exter- nal decoupling capacitor of about 0.1 µF is neces- sary). The output loudspeaker section has two switch- able gains of +9dB and +27dB. +9dB LS Gain This gain mode is fully equivalent to PIAFE ST5080 behaviour. LS+ and LS- outputs are capable of driving output power level up to 80 mW into 50 Ω differentially connected load impedance at low distortion meet- ing PCM channel specifications. When the signal source is a Ring squarewave signal, power levels up to approximatively 200 mW can be delivered. +27dB LS Gain Additional gain of 18dB has the purpose to in- crease the undistorted output power up to 150mW typical with digital input DR ranging from -12dBm0 to +3dBm0. Output DC offset is limited by high pass filter with 35Hz cut frequency (with LS gain = +9dB cut fre- quency = 9Hz) Anti-acoustic feed-back for loudspeaker to hand- set microphone loop with squelch effect: on chip ST5088 7/33 |
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