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ST5090TQFPTR Arkusz danych(PDF) 6 Page - STMicroelectronics |
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6 / 29 page be set by writing to bits 4 to 7 in register CR6. At- tenuations in the range 0 to -30 dB relative to the maximum level in 2 dB step can be programmed. The input of this programmable amplifier is the sum of several signals which can be selected by writing to register CR4.: - Receive speech signal which has been de- coded and filtered, - Internally generated tone signal, (Tone ampli- tude is programmed with bits 4 to 7 of register CR7), - Sidetone signal, the amplitude of which is pro- grammed with bits 0 to 3 of register CR5 VFR+ and VFR- outputs are capable of driving output power level up to 66mW into differentially con- nected load impedance of 30 Ω. Piezoceramic re- ceivers up to 50nF can also be driven. Differential outputs VLr+,VLr- are intended to di- rectly drive an extra output. Preceding the outputs is a programmable attenuation amplifier, which must be set by writing to bits 0 to 3 in register CR6. Attenuations in the range 0 to -30 dB rela- tive to the maximum level in 2.0 dB step can be programmed. The input of this programmable am- plifier can be the sum of signals which can be se- lected by writing to register CR4: - Receive speech signal which has been de- coded and filtered, - Internally generated tone signal, (Tone ampli- tude is programmed with bits 4 to 7 of register CR7), - Sidetone signal, the amplitude of which is pro- grammed with bits 0 to 3 of register CR5. VLr+ and VLr- outputs are capable of driving output power level up to 66mW into differentially con- nected load impedance of 30 Ω. Piezoceramic re- ceivers up to 50nF can also be driven. BUZZER OUTPUT: Single ended output BZ is intended to drive a buzzer, via an external BJT, with a squarewave pulse width modulated (PWM) signal the fre- quency of which is stored into register CR8. For some applications it is also possible to ampli- tude modulate this PWM signal with a square- wave signal having a frequency stored in register CR9. Maximum load for BZ is 5k Ω and 50pF. I.6 Digital Interface (Fig. 1) FS Frame Sync input determines the beginning of frame. It may have any duration from a single cy- cle of MCLK to a squarewave. Three different re- lationships may be established between the Frame Sync input and the first time slot of frame by setting bits DM1 and DM0 in register CR1. Non delayed data mode is similar to long frame timing on ST5080A: first time slot begins nomi- nally coincident with the rising edge of FS. Alter- native is to use delayed data mode, which is simi- lar to short frame sync timing on ST5080A, in which FS input must be high at least a half cycle of MCLK earlier the frame beginning. In the case of companded code only (bit CM = 1 in register CRO) a time slot assignment circuit on chip may be used with all timing modes, allowing connec- tion to one of the two B1 and B2 voice data chan- nels. Two data formats are available: in Format 1, time slot B1 corresponds to the 8 MCLK cycles follow- ing immediately the rising edge of FS, while time slot B2 corresponds to the 8 MCLK cycles follow- ing immediately time slot B1. In Format 2, time slot B1 is identical to Format 1. Time slot B2 appears two bit slots after time slot B1. This two bits space is left available for inser- tion of the D channel data. Data format is selected by bit FF (2) in register CR0. Time slot B1 or B2 is selected by bit TS (1) in Control Register CR1. Bit EN (2) in control register CR1 enables or dis- ables the voice data transfer on DX and DR as appropriate. During the assigned time slot, DX output shifts data out from the voice data register on the rising edges of MCLK in the case of de- layed and non-delayed normal modes or on the falling edges of MCLK in the case of non-delayed reverse mode. Serial voice data is shifted into DR input during the same time slot on the falling edges of MCLK in the case of delayed and non- delayed normal modes or on the rising edges of MCLK in the case of non-delayed reverse mode. DX is in the high impedance Tristate condition when in the non selected time slots. I.7 Control Interface: Control information or data is written into or read- back from ST5090 via the serial control port con- sisting of control clock CCLK, serial data input CI and output CO, and Chip Select input, CS-. All control instructions require 2 bytes as listed in Ta- ble 1, with the exception of a single byte power- up/down command. To shift control data into ST5090, CCLK must be pulsed high 8 times while CS- is low. Data on CI input is shifted into the serial input register on the rising edge of each CCLK pulse. After all data is shifted in, the content of the input shift register is decoded, and may indicate that a 2nd byte of control data will follow. This second byte may either be defined by a second byte-wide CS- pulse or may follow the first contiguously, i.e. it is not mandatory for CS- to return high in between the first and second control bytes. At the end of the 2nd control byte, data is loaded into the ap- ST5090 6/29 |
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