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AD4600ACPZ-R7 Arkusz danych(PDF) 5 Page - Analog Devices |
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AD4600ACPZ-R7 Arkusz danych(HTML) 5 Page - Analog Devices |
5 / 28 page ADN4600 Rev. 0 | Page 5 of 5 TIMING SPECIFICATIONS Table 2. I2C Timing Parameters Parameter Min Max Unit Description fSCL 0 400 kHz SCL clock frequency tHD;STA 0.6 N/A μs Hold time for a start condition tSU;STA 0.6 N/A μs Setup time for a repeated start condition tLOW 1.3 N/A μs Low period of the SCL clock tHIGH 0.6 N/A μs High period of the SCL clock tHD;DAT 0 N/A μs Data hold time tSU;DAT 10 N/A ns Data setup time tr 1 300 ns Rise time for both SDA and SCL tf 1 300 ns Fall time for both SDA and SCL tSU;STO 0.6 N/A μs Setup time for a stop condition tBUF 1 N/A ns Bus-free time between a stop and a start condition CIO 5 7 Pf Capacitance for each I/O pin I2C Timing Specifications S P Sr S SDA SCL tf tf tf tf tBUF tLOW tHD:STA tHD:DAT tHIGH tSU:DAT tSU:STA tSU:STO tHD:STA Figure 2. I2C Timing Diagram |
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