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M40Z111MH6F Arkusz danych(PDF) 10 Page - STMicroelectronics

Numer części M40Z111MH6F
Szczegółowy opis  5V or 3V NVRAM supervisor for up to two LPSRAMs
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Producent  STMICROELECTRONICS [STMicroelectronics]
Strona internetowa  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

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Operation
M40Z111, M40Z111W
10/21
Table 2.
Power down/up AC characteristics
2.2
VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage
fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if
capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (as shown in
Figure 6) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on VCC that drive it to values below VSS by as much as
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, STMicroelectronics recommends
connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS).
Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is
recommended for surface mount.
Symbol
Parameter(1)
1.
Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V or 2.7 to 3.6V (except where
noted).
Min
Max
Unit
tF
(2)
2.
VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring
until 200 µs after VCC passes VPFD (min).
VPFD (max) to VPFD (min) VCC fall time
300
µs
tFB
(3)
3.
VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
VPFD (min) to VSS VCC fall time
10
µs
tR
VPFD (min) to VPFD (max) VCC rise time
10
µs
tRB
VSS to VPFD (min) VCC rise time
1
µs
tEDL
Chip enable propagation delay
M40Z111
15
ns
M40Z111W
20
ns
tEDH
Chip enable propagation delay
M40Z111
10
ns
M40Z111W
20
ns
tER
(4)
4.
tER (min) = 20ms for industrial temperature range - grade 6 device.
Chip enable recovery
40
200
ms
tWPT
Write protect time
M40Z111
40
150
µs
M40Z111W
40
250
µs


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