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AD1882AJCPZ Arkusz danych(PDF) 10 Page - Analog Devices |
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AD1882AJCPZ Arkusz danych(HTML) 10 Page - Analog Devices |
10 / 20 page Rev. 0 | Page 10 of 20 | August 2008 AD1882A POWER AND GROUND DVIO 3.3 V ± 10% or DVIO 1.5 V ± 5.5% 4 I Connect to the I/O Voltage Used for the HD Audio Controller Signals. DVGPIO 3 I Connect to 3.3 V digital supply to power the GPIO and S/PDIF pins. DVSS 7 I Digital Supply Return (Ground). DVDD (3.3 V) 9 I Digital Supply Voltage 3.3 V. This is regulated down to DVCORE on Pin 1 to supply the internal digital core internal to the AD1882A. AVDD (3.3 V) 25, 38 I CAUTION: DO NOT APPLY 5.0 V TO THESE PINS! Analog Supply Voltage 3.3 V ONLY. Note: AVDD supplies should be well regulated and filtered as supply noise degrades audio performance. MIC_BIAS_IN 33 I Source Power for Microphone Bias Circuitry. Connect this pin to 5.0 V via a low-pass filter. When connected this way, the AD1882A is capable of providing 3.9 V as a mic bias to all of the MIC_BIAS pins. If 5 V is not available, connect this pin to 3.3 V (AVDD) via a low-pass filter. AVSS 26, 42 I Analog Supply Return (Ground). AVSS should be connected to DVSS using a conductive trace under, or close to, the AD1882A. Table 6. AD1882A Pin Descriptions (Continued) Mnemonic Pin No. Function Description The symbols used in this table are defined as: I = input, O = output, LI = line level input, LO = line level output, HP = output capable of driving headphone load, MIC = input supports microphones with MIC bias and boost amplifier, SWAP = outputs can swap L/R channels (typically used to support C/LFE or shared C/LFE function). |
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