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TS7514CP Arkusz danych(PDF) 7 Page - STMicroelectronics |
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TS7514CP Arkusz danych(HTML) 7 Page - STMicroelectronics |
7 / 19 page CARRIER LEVEL DETECTOR - Output Level Detection conditions The DCD signal detector output is set to logic state 0 if the RMS value of the demodulator input signal is greater than N1. The DCD output has logic state 1 if the RMS value is less than N2. The detector has an hysteresis effect : N1 - N2. - Timing Detection Requirements Signal detection time constants at the DCD out- put comply with CCITT Recommendation V.23. Modu lation Ratio DCD Transition CCITT V.23 (min) Min. Max. CCITT V.23 (max) Unit 1200bps t1 t2 10 5 10 5 20 15 20 15 ms ms 75bps (Note 1) t1 t2 0 15 15 15 40 40 80 80 ms ms Note 1 : wide band Rx filter used (see Figure 7c). N1 0V N1 LINE DCD t 2 t 1 Note : When delays are bypassed (see RPRX register programming) response time ranges from 0 to 5ms in receive mode at 1200bps, and from 0 to 10ms at 75bps. Figure 4 : Signal Detection Time Out PROGRAMMING REGISTER (RPROG) Address Data Selected Mode (note 1) D7 D6 D5 D4 D3 D2 D1 D0 X 000 0 0 X X 0 1 0 1 The most significant bit (D7) is not used when decoding control register addresses. 0 X 0 1 Control register addressing is enabled when D7 = 0 (see note 2). 0 X 1 0 Control register addressing is enabled when D7 = 1 (see note 2). 0 0 X X Reception positioned in the channel opposite tothe transmission channel controlled by MC/BC 0 1 X X Reception positioned in the same channel as transmission (see note 3). 1 X X X Programming inhibited in normal operating mode. This mode is used for testing purposes. Notes : 1. RPROG is set to 0000 on power-up. 2. Excepted for RPROG register whose address is always 000, regardless of D0 and D1. 3. This mode allows either full duplex operation on a 4-wire line, or circuit testing with external Tx/Rx loopback. TS7514 7/19 |
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