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TS68HC901CFN5 Arkusz danych(PDF) 5 Page - STMicroelectronics |
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TS68HC901CFN5 Arkusz danych(HTML) 5 Page - STMicroelectronics |
5 / 42 page RS1-RS5: (A1-A5) Register Address Bus (inputs). The ad- dress bus is used to address one of the internal registers during a read or write cycle. D0-D7 : Data Bus (bi-directional, tri-stateable). This bus is used to receive data from or transmit data to the MFP’s internal regis- ters during a processor read or write cy- cle. During an interrupt acknowledge cy- cle, the data bus is used to pass a vector number to the processor. Since the MFP is an 8-bit peripheral, the MFP could be located on either the upper or lower por- tion of the 16-bit data bus (even or odd address). However, during an interrupt acknowledge cycle, the vector number passed to the processor must be located in the low byte of the data word. As a re- sult, D0-D7 of the MFP must be connec- ted to the low eight bits of the processor data bus, placing MFP registers at odd addresses if vectored interrupt are to be used. CLK : The clock input is a single-phase TTL compatible signal used for internal ti- ming . This input should not be gated off at any time and must conform to mini- mum and maximum pulse width times. The clock is not necessarily the system clock in frequency nor phase. When the bus is multiplexed (MPX=1), an address strobe signal is connected to this pin. In the non multiplexed mode (MPX=0), this input is connected to the system clock when used with a 68000 processor type or to VSS (0VDC) when used with a 6800 processor type. RESET : Device reset. (input, active low). Reset disables the USART receiver and trans- mitter, stops all timers and forces the ti- mer outputs low, disables all interrupt channels and clears any pending inter- rupts. The General Purpose Interrupt/I/O lines will be placed in the tri-state input mode. All internal registers (except the ti- mer, USART data registers, and transmit status register) will be cleared. MPX : This input selects the data bus mode: MPX = 0 : non multiplexed mode MPX = 1 : multiplexed mode. The register select lines RS1-RS5 and the data bus D0-D7 are multiplexed. An address strobe must be connected to the CLK pin. IRQ : Interrupt Request (output, active low, o- pen drain). This output signals the pro- cessor that an interrupt is pending from the CMFP. These are 16 interrupt chan- nels that can generate an interrupt re- quest. Clearing the interrupt pending re- gisters (IPRA and IPRB) or clearing the interrupt mask registers (IMRA and IMRB) will cause IRQ to be negated. IRQ will also be negated as the result of an in- terrupt acknowledge cycle, unless addi- tional i nterrupts are pending in the CM FP. Ref er to par agraph INTER- RUPTS for further information. IACK : Interrupt Acknowledge (input, active l ow ). IACK i s us ed t o s ignal t he TS68HC901 that the CPU is acknow- ledging an interrupt. CS and IACk must not be asserted at the same time. IEI : Interrupt Enable In (input, active low). IEI is used to signal the TS68HC901 that no higher priority device is requesting inter- rupt service. IEO : Interrupt Enable Out (output, active low). IEO is used to signal lower priority peri- pherals that neither the TS68HC901 nor another higher priority peripheral is re- questing interrupt service. I0-I7 : Ge neral Purpose Interrupt I/O lines. These lines may be used as interrupt in- puts and/or I/O lines. When used as inter- rupt inputs, their active edge is program- mable. A data direction register is used to define which lines are to be Hi-Z inputs and which lines are to be push-pull TTL compatible outputs. SO : Serial Output. This is the output of the U- SART transmitter. SI : Serial Input. This is the input to the U- SART receiver. RC : Receiver Clock. This input controls the serial bit rate of the USART receiver. TC : Transmitter Clock. This input controls the serial bit rate of the USART transmitter. RR : Receiver Ready. (output, active low) DMA output for receiver, which reflects the status of Buffer Full in port number 15. TR : Transmitter Ready. (output, active low) DMA output for transmitter, which re- flects the status of Buffer Empty in port number 16. ® TS68HC901 5/42 |
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