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MC-ACT-UARTF-NET Arkusz danych(PDF) 4 Page - Actel Corporation |
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MC-ACT-UARTF-NET Arkusz danych(HTML) 4 Page - Actel Corporation |
4 / 6 page Fast UART Memec Design February 25, 2003 4 Optimized for Accuracy: The worst case accuracy can be calculated by simply inversing the value n. Therefore, a value larger than 100 will guarantee accuracy better than 1%, values larger than 1000 produce results better than 0.1%. Jitter: The faster the baudrate, the better the accuracy, but more relative jitter is added. Maximum absolute jitter is always equal 1/fclk. Serial Interface The serial interface includes the receive and transmit path separately. It is full a duplex solution, receive and transmit is possible at the same time. Transmitter Interface For transmitting data, a parallel event controlled interface is used. It is an efficient way to embed the MC-ACT- UARTF in systems as well as connecting simple or complex specific interfaces, including queues etc., to it. The transmitter path stores the incoming byte in the shift register by means of the fuart_tx_we signal and starts the transmitting activity. fuart_tx_busy goes high also and remains high until the data is sent. Receiver Interface For receiving data, a similar type of interface is used as in the transmitter path The receiver path contains several checks and special features. First, the level at the fuart_rx_pin is watched. When a falling edge is detected, the receiver is started. A reception is started only when the start bit after a falling edge is detected low. If parity is enabled, it is checked and event failures are reported on fuart_par_error. Missing stop bits (level not zero) are reported as format checks. In all error cases, the data byte is aborted and the error reason is reported. Please note that fuart_rx_ready is not asserted when error reporting is done. Device Requirements Family Device Utilization Performance COMB SEQ Total SX-A SX08A-3 274 (54%) 104 (41%) 378 (50%) 142 MHz ProASIC PLUS APA075-STD n/a n/a 659 (22%) 70 MHz Axcelerator AX500-3 270 (5%) 104 (4%) 374 (5%) 153 MHz Table 1: Device Utilization and Performance Verification and Compliance Complete functional and timing simulation has been performed on the UART-F using ModelSim 5.5d. The UART-F core has been used successfully in customer designs. |
Podobny numer części - MC-ACT-UARTF-NET |
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