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74LV161284DGGRE4 Arkusz danych(PDF) 3 Page - Texas Instruments

Numer części 74LV161284DGGRE4
Szczegółowy opis  19-BIT BUS INTERFACE
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74LV161284DGGRE4 Arkusz danych(HTML) 3 Page - Texas Instruments

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SN74LV161284
19-BIT BUS INTERFACE
SCLS426C – OCTOBER 1998 – REVISED NOVEMBER 2002
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range: VCC CABLE
–0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCC
–0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input and output voltage range, VI and VO: Cable side (see Notes 1 and 2)
–2 V to 7 V
. . . . . . . . . . . . . . . . . .
Peripheral side (see Note 1)
–0.5 V to VCC + 0.5 V
. . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC )
±20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC)
±50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC)
±50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each VCC or GND
±200 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output high sink current, ISK (VO = 5.5 V and VCC CABLE = 5.5 V)
65 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
θJA (see Note 3): DGG package
70
°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package
63
°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg
–65
°C to 150°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The ac input voltage pulse duration is limited to 40 ns if the amplitude is more negative than –0.5 V.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
MIN
MAX
UNIT
VCC CABLE
Supply voltage for the cable side, VCC CABLE ≥ VCC
4.5
5.5
V
VCC
Supply voltage
4.5
5.5
V
A, DIR, HD, and PERI LOGIC IN
VCC × 0.7
VIH
High level input voltage
B
2
V
VIH
High-level input voltage
C14–C17
2.3
V
HOST LOGIC IN
2.6
A, DIR, HD, and PERI LOGIC IN
VCC × 0.3
VIL
Low level input voltage
B
0.8
V
VIL
Low-level input voltage
C14–C17
0.8
V
HOST LOGIC IN
1.6
VI
Input voltage
Peripheral side
0
VCC
V
VI
Input voltage
Cable side
0
5.5
V
VO
Open-drain output voltage
B, Y, and PERI LOGIC OUT (HD low)
0
5.5
V
B and Y outputs (HD high)
–14
IOH
High-level output current
A outputs and HOST LOGIC OUT
–8
mA
PERI LOGIC OUT
–0.5
B and Y outputs
14
IOL
Low-level output current
A outputs and HOST LOGIC OUT
8
mA
PERI LOGIC OUT
84
TA
Operating free-air temperature
–40
85
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.


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