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74LV161284DGGRE4 Arkusz danych(PDF) 6 Page - Texas Instruments

Numer części 74LV161284DGGRE4
Szczegółowy opis  19-BIT BUS INTERFACE
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74LV161284DGGRE4 Arkusz danych(HTML) 6 Page - Texas Instruments

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SN74LV161284
19-BIT BUS INTERFACE
SCLS426C – OCTOBER 1998 – REVISED NOVEMBER 2002
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
tPHL
tPLH
From
B or Y Output
Under Test
SLEW RATE A-TO-B OR A-TO-Y LOAD (Totem Pole)
VOLTAGE WAVEFORMS MEASURED AT TP1
PROPAGATION DELAY TIMES (A to B)
VCC
VOH
VOL
0 V
62
CL = 50 pF
(see Note A)
TP1
VCC
CL = 50 pF
(see Note A)
Sink Load
Source Load
VOH – 1.4 V
62
tPHL
tPLH
Input
(see Note B)
Output
(see Note B)
VOL + 1.4 V
tw
A-TO-B LOAD OR A-TO-Y LOAD (Open Drain)
VOLTAGE WAVEFORMS MEASURED AT TP1, B SIDE
VCC
VOH
VOL
0 V
2 V
2 V
0.8 V
0.8 V
tr
tf
TP1
From
B or Y Output
CL = 50 pF
(see Note A)
500
VCC
NOTES: A. CL includes probe and jig capacitance.
B. Input rise and fall times are 3 ns, 150 ns < pulse duration < 10
µs for both low-to-high and high-to-low transitions.
Slew rate is measured between 0.4 V and 1.9 V for the rising edge and between 95% VCC and 50% VCC for the falling edge.
C. Input rise and fall times are 3 ns. Rise and fall times (open drain) < 120 ns.
D. The outputs are measured one at a time with one transition per measurement.
VCC/2
VCC/2
VCC/2
VCC/2
Input
(see Note C)
Output
(see Note C)
Figure 1. Load Circuits and Voltage Waveforms


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