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74LV161284DGGRE4 Arkusz danych(PDF) 7 Page - Texas Instruments |
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74LV161284DGGRE4 Arkusz danych(HTML) 7 Page - Texas Instruments |
7 / 7 page SN74LV161284 19-BIT BUS INTERFACE SCLS426C – OCTOBER 1998 – REVISED NOVEMBER 2002 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION From Output Under Test CL = 50 pF (see Note A) LOAD CIRCUIT S1 VCC × 2 Open GND 500 Ω 500 Ω Output Control Output Waveform 1 S1 at VCC × 2 V (see Note C) Output Waveform 2 S1 at GND (see Note C) VOL VOH tPZL tPZH tPLZ tPHZ VCC/2 VCC/2 VCC 0 V VCC/2 VOL + 0.3 V VCC/2 VOH – 0.3 V 0 V VCC VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VCC × 2 GND TEST S1 NOTES: A. CL includes probe and jig capacitance. B. Input rise and fall times are 3 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. Input rise and fall times are 3 ns, 150 ns < pulse duration < 10 µs for both low-to-high and high-to-low transitions. E. The outputs are measured one at a time with one transition per measurement. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. tPHL tPLH VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (B to A) 3 V VOH VOL 0 V VCC/2 Input (see Note B) Output VCC/2 B-TO-A LOAD (Totem Pole) tPHL tPLH From B or Y Output Under Test A-TO-B LOAD OR A-TO-Y LOAD (Totem Pole) VOLTAGE WAVEFORMS MEASURED AT TP1 PROPAGATION DELAY TIMES (A to B) VCC VOH VOL 0 V 500 Ω CL = 50 pF (see Note A) TP1 VCC CL = 50 pF (see Note A) Sink Load Source Load VOH – 1.4 V 500 Ω tPHL tPLH Input (see Note D) Output (see Note D) VOL + 1.4 V tw 1.5 V 1.5 V VCC/2 VCC/2 Figure 2. Load Circuit and Voltage Waveforms |
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