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74LV161284DGGRE4 Arkusz danych(PDF) 2 Page - Texas Instruments |
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74LV161284DGGRE4 Arkusz danych(HTML) 2 Page - Texas Instruments |
2 / 7 page SN74LV161284 19-BIT BUS INTERFACE SCLS426C – OCTOBER 1998 – REVISED NOVEMBER 2002 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FUNCTION TABLE INPUTS OUTPUT MODE DIR HD OUTPUT MODE L L Open drain A9–A13 to Y9–Y13 and PERI LOGIC IN to PERI LOGIC OUT L L Totem pole B1–B8 to A1–A8 and C14–C17 to A14–A17 L H Totem pole B1–B8 to A1–A8, A9–A13 to Y9–Y13, PERI LOGIC IN to PERI LOGIC OUT, and C14–C17 to A14–A17 H L Open drain A1–A8 to B1–B8, A9–A13 to Y9–Y13, and PERI LOGIC IN to PERI LOGIC OUT H L Totem pole C14–C17 to A14–A17 H H Totem pole A1–A8 to B1–B8, A9–A13 to Y9–Y13, C14–C17 to A14–A17, and PERI LOGIC IN to PERI LOGIC OUT logic diagram (positive logic) See Note B See Note B See Note A B1–B8 Y9–Y13 PERI LOGIC OUT C14–C17 HOST LOGIC IN VCC CABLE DIR HD A1–A8 A9–A13 PERI LOGIC IN A14–A17 HOST LOGIC OUT 42 48 1 19 24 30 25 NOTES: A. The PMOS prevents backdriving current from the signal pins to VCC CABLE when VCC CABLE is open or at GND. B. The PMOS prevents backdriving current from the signal pins to VCC CABLE when VCC CABLE is open or at GND. The PMOS is turned off when the associated driver is in the low state. |
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