TP3056B

MONOLITHIC SERIAL INTERFACE

COMBINED PCM CODEC AND FILTER

SLWS072A – MAY 1998 – REVISED AUGUST 1998

3

POST OFFICE BOX 655303

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

ANLG GND

2

Analog ground. All signals are referenced to ANLG GND.

ASEL

7

I

A-law/

µ-law select. When ASEL is connected to VCC, A-law is selected. When ASEL is connected to GND or VBB,

µ-law is selected.

BCLK

10

I

Transmit/receive bit clock. BCLK shifts PCM data out on DX during transmit and shifts PCM data in through DR

during receive. BCLK can vary from 64 kHz to 2.048 MHz, but must be synchronous with MCLK.

DR

6

I

Receive data input. PCM data is shifted into DR at the trailing edge of the BCLK following the FSR leading edge.

DX

11

O

DX is the 3-state PCM data output that is enabled by FSX. Data is shifted out on the rising edge of BCLK.

FSR

5

I

Receive-frame sync pulse input. FSR enables BCLK to shift PCM data in DR. FSR is an 8-kHz pulse train (see

Figures 1 and 2 for timing details).

FSX

12

I

Transmit-frame sync pulse. FSX enables BCLK to shift out the PCM data on DX. FSX is an 8-kHz pulse train (see

Figures 1 and 2 for timing details).

GSX

14

O

Analog output of the transmit input amplifier. GSX is used to set gain externally.

MCLK

9

I

Transmit/receive master clock. MCLK must be 2.048 MHz.

PDN

8

I

Power down. When PDN is connected high, the device is powered down. When PDN is connected low or left

floating, the device is powered up. PDN is internally tied low.

TSX

13

O

Transmit channel time-slot strobe. TSX is an open-drain output that pulses low during the encoder time slot.

VBB

1

Negative power supply. VBB = – 5 V ± 5%

VCC

4

Positive power supply. VCC = 5 V ± 5%

VFRO

3

O

Analog output of the receive channel power amplifier

VFXI +

16

I

Noninverting input of the transmit input amplifier

VFXI –

15

I

Inverting input of the transmit input amplifier