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AD7193BRUZ Arkusz danych(PDF) 2 Page - Analog Devices

Numer części AD7193BRUZ
Szczegółowy opis  4-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
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AD7193BRUZ Arkusz danych(HTML) 2 Page - Analog Devices

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AD7193
Rev. A | Page 2 of 56
TABLE OF CONTENTS
Features .............................................................................................. 1
 
Applications....................................................................................... 1
 
General Description ......................................................................... 1
 
Functional Block Diagram .............................................................. 1
 
Revision History ............................................................................... 2
 
Specifications..................................................................................... 3
 
Timing Characteristics ................................................................ 7
 
Absolute Maximum Ratings............................................................ 9
 
Thermal Resistance ...................................................................... 9
 
ESD Caution.................................................................................. 9
 
Pin Configuration and Function Descriptions........................... 10
 
Typical Performance Characteristics ........................................... 12
 
RMS Noise and Resolution............................................................ 15
 
Sinc4 Chop Disabled................................................................... 15
 
Sinc3 Chop Disabled................................................................... 16
 
Fast Settling ................................................................................. 17
 
On-Chip Registers .......................................................................... 18
 
Communications Register......................................................... 19
 
Status Register ............................................................................. 20
 
Mode Register ............................................................................. 21
 
Configuration Register .............................................................. 24
 
Data Register ............................................................................... 26
 
ID Register................................................................................... 26
 
GPOCON Register ..................................................................... 26
 
Offset Register............................................................................. 27
 
Full-Scale Register ...................................................................... 27
 
ADC Circuit Information.............................................................. 28
 
Overview...................................................................................... 28
 
Analog Input Channel ............................................................... 29
 
Programmable Gain Array (PGA) ........................................... 29
 
Reference ..................................................................................... 29
 
Reference Detect......................................................................... 30
 
Bipolar/Unipolar Configuration .............................................. 30
 
Data Output Coding .................................................................. 30
 
Burnout Currents ....................................................................... 30
 
Channel Sequencer .................................................................... 30
 
Digital Interface.......................................................................... 31
 
Reset ............................................................................................. 35
 
System Synchronization ............................................................ 35
 
Enable Parity ............................................................................... 35
 
Clock ............................................................................................ 35
 
Bridge Power-Down Switch...................................................... 35
 
Temperature Sensor ................................................................... 36
 
Logic Outputs ............................................................................. 36
 
Calibration................................................................................... 36
 
Digital Filter .................................................................................... 38
 
Sinc4 Filter (Chop Disabled) ..................................................... 38
 
Sinc3 Filter (Chop Disabled) ..................................................... 40
 
Chop Enabled (Sinc4 Filter) ...................................................... 42
 
Chop Enabled (Sinc3 Filter) ...................................................... 44
 
Fast Settling Mode (Sinc4 Filter)............................................... 45
 
Fast Settling Mode (Sinc3 Filter)............................................... 47
 
Fast Settling Mode (Chop Enabled)......................................... 49
 
Summary of Filter Options ....................................................... 50
 
Grounding and Layout .................................................................. 51
 
Applications Information .............................................................. 52
 
Flowmeter.................................................................................... 52
 
Outline Dimensions ....................................................................... 53
 
Ordering Guide .......................................................................... 53
 
REVISION HISTORY
9/09—Rev. 0 to Rev. A
Changes to Internal/External Clock, Internal Clock Frequency
Parameter, Table 1............................................................................. 5
Changes to Figure 6 and Figure 7................................................. 12
Changes to Table 6.......................................................................... 15
Changes to Table 9.......................................................................... 16
Changes to Table 12, Table 13, and Table 14............................... 17
Changes to Table 19........................................................................ 22
Changes to Table 22 and Table 23 ................................................ 25
Changes to Offset Register and Full-Scale Register Sections ... 27
Changes to Reference Section....................................................... 29
Changes to Data Output Coding Section.................................... 30
Changes to Sinc4 50 Hz/60 Hz Rejection Section ...................... 39
Changes to Sinc3 50 Hz/60 Hz Rejection Section ...................... 41
Changes to 50 Hz/60 Hz Rejection, Sinc4 Filter Section ........... 45
Changes to Summary of Filter Options Section and Table 35.. 50
7/09—Revision 0: Initial Version


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