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AD9122BCPZ Arkusz danych(PDF) 5 Page - Analog Devices

Numer części AD9122BCPZ
Szczegółowy opis  Dual, 16-Bit, 1200 MSPS, TxDAC짰 Digital-to-Analog Converter
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

AD9122BCPZ Arkusz danych(HTML) 5 Page - Analog Devices

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AD9122
Rev. 0 | Page 5 of 56
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 1.8 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
CMOS INPUT LOGIC LEVEL
Input VIN Logic High (IOVDD = 1.8 V)
1.2
V
Input VIN Logic High (IOVDD = 2.5 V)
1.6
V
Input VIN Logic Low (IOVDD = 1.8 V)
0.6
V
Input VIN Logic Low (IOVDD = 2.5 V)
0.8
V
CMOS OUTPUT LOGIC LEVEL
Output VOUT Logic High
IOVDD = 1.8 V
1.4
V
Output VOUT Logic High
IOVDD = 2.5 V
1.8
V
Output VOUT Logic Low
IOVDD = 1.8 V
0.4
V
Output VOUT Logic Low
IOVDD = 2.5 V
0.4
V
LVDS RECEIVER INPUTS1
Input Voltage Range, VIA or VIB
825
1575
mV
Input Differential Threshold, VIDTH
−100
+100
mV
Input Differential Hysteresis, VIDTHH to VIDTHL
20
mV
Receiver Differential Input Impedance, RIN
80
120
Ω
LVDS Input Rate
See Table 5
DAC CLOCK INPUT (DACCLKP, DACCLKN)
Differential Peak-to-Peak Voltage
100
500
2000
mV
Common-Mode Voltage
Self biased input, ac couple
1.25
V
Maximum Clock Rate
1200
MSPS
REFCLK INPUT (REFCLKP, REFCLKN)
Differential Peak-to-Peak Voltage
100
500
2000
mV
Common-Mode Voltage
1.25
V
REFCLK Frequency (PLL Mode)
1 GHz ≤ fVCO ≤ 26 Hz
15.625
600
MHz
REFCLK Frequency (SYNC Mode)
See Multichip Synchronization section for conditions
0
600
MHz
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK)
40
MHz
Minimum Pulse Width High (tPWH)
12.5
ns
Minimum Pulse Width Low (tPWOL)
12.5
ns
Setup Time, SDI to SCLK (tDS)
1.9
ns
Hold Time, SDI to SCLK (tDH)
0.2
ns
Data Valid, SDO to SCLK (tDV)
23
ns
Setup Time, CS to SCLK (tDCSB)
1.4
ns
1 LVDS receiver is compliant to the IEEE 1596 reduced range link, unless otherwise noted.
DIGITAL INPUT DATA TIMING SPECIFICATIONS
Table 3.
Parameter
Min
Typ
Max
Unit
LATENCY (DACCLK Cycles)
1× Interpolation (With or Without Modulation)
64
Cycles
2× Interpolation (With or Without Modulation)
135
Cycles
4× Interpolation (With or Without Modulation)
292
Cycles
8× Interpolation (With or Without Modulation)
608
Cycles
Inverse Sinc
20
Cycles
Fine Modulation
8
Cycles
Power-Up Time
260
ms


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