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AD7171 Arkusz danych(PDF) 11 Page - Analog Devices |
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AD7171 Arkusz danych(HTML) 11 Page - Analog Devices |
11 / 16 page AD7171 Rev. 0 | Page 11 of 16 DATA OUTPUT CODING The AD7171 uses offset binary coding. Therefore, a negative full-scale voltage results in a code of 000...000, a zero differential input voltage results in a code of 100...000, and a positive full- scale input voltage results in a code of 111...111. The output code for any analog input voltage can be represented as Code = 2N – 1 × [(VINx/VREF) + 1] where: VINx is the analog input voltage. N = 16 for the AD7171. REFERENCE The AD7171 has a fully differential input capability for the channel. The common-mode range for these differential inputs is GND to VDD. The reference input is unbuffered; therefore, excessive R-C source impedances introduce gain errors. The reference voltage REFIN (REFIN(+) − REFIN(−)) is VDD nominal, but the AD7171 is functional with reference voltages of 0.5 V to VDD. In applications where the excitation (voltage or current) for the transducer on the analog input also drives the reference voltage for the part, the effect of the low frequency noise in the excitation source is removed because the application is ratiometric. If the AD7171 is used in a nonratiometric application, a low noise reference should be used. Recommended 2.5 V reference voltage sources for the AD7171 include the ADR381 and ADR391, which are low noise, low power references. Also note that the reference inputs provide a high impedance, dynamic load. Because the input impedance of each reference input is dynamic, resistor/capacitor combinations on these inputs can cause dc gain errors, depending on the output impedance of the source that is driving the reference inputs. Reference voltage sources such as those recommended above (the ADR391, for example) typically have low output impedances and are, therefore, tolerant to decoupling capacitors on REFIN(+) without introducing gain errors in the system. Deriving the reference input voltage across an external resistor means that the reference input sees a significant external source impedance. External decoupling on the REFIN(±) pins is not recommended in this type of circuit configuration. DIGITAL INTERFACE The serial interface of the AD7171 consists of two signals: SCLK and DOUT/RDY. SCLK is the serial clock input for the device, and data transfers occur with respect to the SCLK signal. The DOUT/RDY pin is dual purpose: it functions as a data ready pin and as a data out pin. DOUT/RDY goes low when a new data-word is available in the output register. A 24-bit word is placed on the DOUT/RDY pin when sufficient SCLK pulses are applied. This consists of a 16-bit conversion result followed by eight status bits. shows the functions of the status bits. Table 8 RDY: ready bit. This bit is set low to indicate that a conversion is available. 0 : This bit is set to 0. ERR: This bit is set to 1 if an error occurred during the conversion. An error occurs when the analog input is outside range. ID1, ID0 : ID bits. These bits indicate the ID number for the AD7171. Bit ID1 is set to 0 and bit ID0 is set to 1 for the AD7171. PAT2, PAT1, PAT0 : status pattern bits. They are set to 101 by default. When the user reads the data from the AD7171, a pattern check can be performed. If the PAT2 to PAT0 bits are different from their default values, the serial transfer from the ADC was not performed correctly. Table 8. Status Bits RDY 0 ERR ID1 ID0 PAT2 PAT1 PAT0 DOUT/RDY is reset high when the conversion is read. If the conversion is not read, DOUT/RDY goes high prior to the data register update to indicate when not to read from the device. This ensures that a read operation is not attempted while the register is being updated. Each conversion can be read only once. The data register is updated for every conversion. So, when a conversion is complete, the serial interface is reset, and the new conversion is placed in the data register. Therefore, the user must ensure that the complete word is read before the next conversion is complete. When PDRST is low, the DOUT/RDY pin is tristated. When PDRST is taken high, the internal clock requires 1 ms, approx- imately, to power up. Following this, the ADC continuously converts. The first conversion requires the complete settling time (see ). DOUT/ Figure 4 RDY goes high when PDRST is taken high and returns low only when a conversion is available. The ADC then converts continuously, subsequent conversions being available at 125 Hz. shows the timing for a read operation from the AD7171. Figure 3 |
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Podobny opis - AD7171 |
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