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AD9148BBPZ Arkusz danych(PDF) 2 Page - Analog Devices

Numer części AD9148BBPZ
Szczegółowy opis  Quad 16-Bit,1 GSPS, TxDAC Digital-to-Analog Converter
Download  73 Pages
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

AD9148BBPZ Arkusz danych(HTML) 2 Page - Analog Devices

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AD9148
Preliminary Technical Data
Rev. PrA | Page 2 of 73
TABLE OF CONTENTS
Features .............................................................................................. 1
 
Applications....................................................................................... 1
 
General Description ......................................................................... 1
 
Product Highlights ........................................................................... 1
 
Typical Signal Chain......................................................................... 1
 
Revision History ............................................................................... 2
 
Functional Block Diagram .............................................................. 3
 
Specifications..................................................................................... 4
 
DC Specifications ......................................................................... 4
 
Input/Output Signal Specifications............................................ 5
 
Digital Input Data Timing Specifications ................................. 6
 
AC Specifications.......................................................................... 7
 
Absolute Maximum Ratings............................................................ 8
 
Thermal Resistance ...................................................................... 8
 
Maximum Safe Power Dissipation ............................................. 8
 
ESD Caution.................................................................................. 8
 
Pin Configurations and Function Descriptions ......................... 10
 
Typical Performance Characteristics ........................................... 14
 
Terminology .................................................................................... 20
 
Serial Peripheral Interface ............................................................. 21
 
General Operation of the Serial Interface ............................... 21
 
Data Format ................................................................................ 21
 
SPI Pin Descriptions .................................................................. 21
 
SPI Options ................................................................................. 22
 
SPI Register Map............................................................................. 23
 
SPI Register Descriptions .......................................................... 25
 
Input Data Ports.............................................................................. 39
 
Dual-Port Mode.......................................................................... 39
 
Single-Port Mode........................................................................ 39
 
Byte Mode.................................................................................... 40
 
Data Interface Options .............................................................. 40
 
FIFO Operation .............................................................................. 41
 
Synchronizing and Resetting the FIFO ................................... 42
 
Monitoring the FIFO Status...................................................... 43
 
Device Synchronization................................................................. 44
 
Synchronizing Multiple Devices .............................................. 44
 
Synchronization with Clock Multiplication ............................... 44
 
Synchronization with Direct Clocking.................................... 46
 
Additional Synchronization Features ...................................... 47
 
Interface Timing ............................................................................. 49
 
Digital Data Path ............................................................................ 50
 
Premodulation ............................................................................ 50
 
Programmable Inverse Sinc Filter............................................ 50
 
Interpolation Filters ................................................................... 51
 
Fine Modulation ......................................................................... 54
 
Clock Generation ........................................................................... 56
 
DAC Input Clock Configurations............................................ 56
 
Driving the CLK_x and REFCLK_x Inputs............................ 56
 
Direct Clocking .......................................................................... 56
 
Clock Multiplication .................................................................. 57
 
Analog Outputs............................................................................... 59
 
Transmit DAC Operation.......................................................... 59
 
Auxiliary DAC Operation ......................................................... 60
 
Interfacing to Modulators ......................................................... 61
 
Device Power Dissipation.............................................................. 63
 
Temperature Sensor ....................................................................... 65
 
Interrupt Request Operation ........................................................ 66
 
Interrupt Service Routine.......................................................... 66
 
Interface Timing Validation.......................................................... 67
 
SED Operation............................................................................ 67
 
SED Example .............................................................................. 67
 
Test Access Port .............................................................................. 68
 
Example Start-Up Routine ............................................................ 71
 
Derived PLL Settings ................................................................. 71
 
Derived NCO Settings ............................................................... 71
 
Start-Up Sequence...................................................................... 71
 
Device Verification Sequence ................................................... 71
 
Outline Dimensions ....................................................................... 72
 
Ordering Guide .......................................................................... 73
 
REVISION HISTORY
4/10—Revision PrA: Preliminary Version


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