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74LV132 Arkusz danych(PDF) 3 Page - NXP Semiconductors |
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74LV132 Arkusz danych(HTML) 3 Page - NXP Semiconductors |
3 / 17 page 74LV132_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 2 July 2009 3 of 17 NXP Semiconductors 74LV132 Quad 2-input NAND Schmitt trigger 6. Pinning information 6.1 Pinning 6.2 Pin description (1) The die substrate is attached to the exposed die pad using conductive die attach material. It cannot be used as a supply pin or input. Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14 132 1A VCC 1B 4B 1Y 4A 2A 4Y 2B 3B 2Y 3A GND 3Y 001aac203 1 2 3 4 5 6 7 8 10 9 12 11 14 13 001aah099 74LV132 Transparent top view VCC(1) 2Y 3A 2B 3B 2A 4Y 1Y 4A 1B 4B 6 9 5 10 4 11 3 12 2 13 terminal 1 index area Table 2. Pin description Symbol Pin Description 1A 1 data input 1B 2 data input 1Y 3 data output 2A 4 data input 2B 5 data input 2Y 6 data output GND 7 ground (0 V) 3Y 8 data output 3A 9 data input 3B 10 data input 4Y 11 data output 4A 12 data input 4B 13 data input VCC 14 supply voltage |
Podobny numer części - 74LV132_09 |
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Podobny opis - 74LV132_09 |
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