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74HC132DTR2G Arkusz danych(PDF) 1 Page - ON Semiconductor |
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74HC132DTR2G Arkusz danych(HTML) 1 Page - ON Semiconductor |
1 / 9 page © Semiconductor Components Industries, LLC, 2007 March, 2007 − Rev. 1 1 Publication Order Number: 74HC132/D 74HC132 Quad 2−Input NAND Gate with Schmitt−Trigger Inputs High−Performance Silicon−Gate CMOS The 74HC132 is identical in pinout to the LS132. The device inputs are compatible with standard CMOS outputs; with pull−up resistors, they are compatible with LSTTL outputs. The HC132 can be used to enhance noise immunity or to square up slowly changing waveforms. Features • Output Drive Capability: 10 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 mA • High Noise Immunity Characteristic of CMOS Devices • In Compliance with the Requirements as Defined by JEDEC Standard No. 7A • ESD Performance: HBM > 2000 V; Machine Model > 200 V • Chip Complexity: 72 FETs or 18 Equivalent Gates • These are Pb−Free Devices Figure 1. Pin Assignment 11 12 13 14 8 9 10 5 4 3 2 1 7 6 B3 Y4 A4 B4 VCC Y3 A3 A2 Y1 B1 A1 GND Y2 B2 MARKING DIAGRAMS HC132 = Device Code A = Assembly Location L, WL = Wafer Lot Y = Year W, WW = Work Week G or G = Pb−Free Package SOIC−14 D SUFFIX CASE 751A HC132G AWLYWW TSSOP−14 DT SUFFIX CASE 948G HC 132 ALYW G G 1 14 See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ORDERING INFORMATION Inputs Output AB Y LL H LH H HLH HH L FUNCTION TABLE 1 14 http://onsemi.com (Note: Microdot may be in either location) |
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