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TL16C550DPFB Arkusz danych(PDF) 7 Page - Texas Instruments |
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TL16C550DPFB Arkusz danych(HTML) 7 Page - Texas Instruments |
7 / 54 page Receiver Buffer Register Divisor Latch (LS) Divisor Latch (MS) Baud Generator Receiver FIFO Line Status Register Transmitter Holding Register Modem Control Register Modem Status Register Line Control Register Transmitter FIFO Interrupt Enable Register Interrupt Identification Register FIFO Control Register Select and Control Logic Interrupt Control Logic S e l e c t Data Bus Buffer SIN SOUT CTS INTRPT C4 D4 C2 C1 A0 D5 D(7 - 0) 5 -3 32-29 Internal Data Bus E5 E4 D1 B5 D3 D2 E1 E2 A1 A2 CS2 MR RD1 WR1 XIN XOUT S e l e c t Receiver Shift Register Receiver Timing and Control Transmitter Timing and Control Transmitter Shift Register Modem Control Logic 8 A5 E3 VCC VSS Power Supply RTS C5 Autoflow Control (AFE) 8 8 8 8 8 8 8 TL16C550D ,, TL16C550DI www.ti.com .................................................................................................................................................. SLLS597E – APRIL 2004 – REVISED DECEMBER 2008 FUNCTIONAL BLOCK DIAGRAM (For ZQS Package) Copyright © 2004–2008, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): TL16C550D TL16C550DI |
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