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TL16C2550IRHBRG4 Arkusz danych(PDF) 8 Page - Texas Instruments |
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TL16C2550IRHBRG4 Arkusz danych(HTML) 8 Page - Texas Instruments |
8 / 47 page www.ti.com Receiver Buffer Register Divisor Latch (LS) Divisor Latch (MS) Baud Generator Receiver FIFO Line Status Register Transmitter Holding Register Modem Control Register Modem Status Register Line Control Register Transmitter FIFO Interrupt Enable Register Interrupt Identification Register FIFO Control Register Select and Control Logic Interrupt Control Logic S e l e c t Data Bus Buffer RXA, B TXA, B CTSA, B DTRA, B DSRA, b CDA,B RIA, B OPA, B INTA, B 38, 23 34, 35 39, 20 40, 16 41, 21 32, 9 30, 29 7, 8 5,4 A0 28 D(7 −0) 3 −1 48−44 Internal Data Bus 27 26 10 11 14 36 19 15 13 43 31 A1 A2 CSA CSB XTAL2 RESET IOR IOW XTAL1 TXRDYA RXRDYA S e l e c t Receiver Shift Register Receiver Timing and Control Transmitter Timing and Control Transmitter Shift Register Modem Control Logic 8 42 17 VCC GND Power Supply RTSA, B 33, 22 Autoflow Control (AFE) 8 8 8 8 8 8 8 6 18 TXRDYB RXRDYB Crystal OSC Buffer TL16C2550 SLWS161D – JUNE 2005 – REVISED OCTOBER 2006 A. Pin numbers shown are for 48-pin TQFP PFB package. Figure 5. Functional Block Diagram 8 Submit Documentation Feedback |
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