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AD9125 Arkusz danych(PDF) 5 Page - Analog Devices

Numer części AD9125
Szczegółowy opis  Dual, 16-Bit, 1000 MSPS, TxDAC Digital-to-Analog Converter
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

AD9125 Arkusz danych(HTML) 5 Page - Analog Devices

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AD9125
Rev. 0 | Page 5 of 5
6
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
CMOS DATA INPUTS
Input VIN Logic High
1.2
V
Input VIN Logic Low
0.6
V
Maximum Bus Speed
250
MHz
SERIAL PORT OUTPUT LOGIC LEVELS
Output VOUT Logic High
IOVDD = 1.8 V
1.4
V
IOVDD = 2.5 V
1.8
V
IOVDD = 3.3 V
2.0
V
Output VOUT Logic Low
IOVDD = 1.8 V
0.4
IOVDD = 2.5 V
0.4
V
IOVDD = 3.3 V
0.4
V
SERIAL PORT INPUT LOGIC LEVELS
Input VIN Logic High
IOVDD = 1.8 V
1.2
V
IOVDD = 2.5 V
1.6
V
IOVDD = 3.3 V
2.4
V
Input VIN Logic Low
IOVDD = 1.8 V
0.6
V
IOVDD = 2.5 V
0.8
V
IOVDD = 3.3V
0.8
V
DACCLK INPUT (DACCLKP, DACCLKN)
Differential Peak-to-Peak Voltage
100
500
2000
mV
Common-Mode Voltage
Self biased input, ac couple
1.25
V
Maximum Clock Rate
1000
MHz
REFCLK INPUT (REFCLKP, REFCLKN)
Differential Peak-to-Peak Voltage
100
500
2000
mV
Common-Mode Voltage
1.25
V
REFCLKx Frequency, PLL Mode
1 GHz ≤ fVCO ≤ 2.1 GHz
15.625
600
MHz
REFCLKx Frequency, SYNC Mode
See the Multichip Synchronization section for conditions
0
600
MHz
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK)
40
MHz
Minimum Pulse Width High (tPWH)
12.5
ns
Minimum Pulse Width Low (tPWOL)
12.5
ns
Setup Time, SDI to SCLK (tDS)
1.9
ns
Hold Time, SDI to SCLK (tDH)
0.2
ns
Data Valid, SDO to SCLK (tDV)
2.3
ns
Setup Time, CS to SCLK (tDCS)
1.4
ns
LATENCY AND POWER-UP TIMING SPECIFICATIONS
Table 3.
Parameter
Min
Typ
Max
Unit
LATENCY (DACCLK Cycles)
1× Interpolation (with or Without Modulation)
64
Cycles
2× Interpolation (with or Without Modulation)
135
Cycles
4× Interpolation (with or Without Modulation)
292
Cycles
8× Interpolation (with or Without Modulation)
608
Cycles
Inverse Sinc
20
Cycles
Fine Modulation
8
Cycles
Power-Up Time
260
ms


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