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ISL1221IUZ-T Arkusz danych(PDF) 10 Page - Intersil Corporation

Numer części ISL1221IUZ-T
Szczegółowy opis  Low Power RTC with Battery Backed
Download  24 Pages
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Producent  INTERSIL [Intersil Corporation]
Strona internetowa  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL1221IUZ-T Arkusz danych(HTML) 10 Page - Intersil Corporation

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10
FN6316.0
June 22, 2006
Event Detect Timing Diagram with
Sampling Mode Enabled
Case 1, Switch Opened Before Ipu
Case 2, Switch Opened After Ipu
Case 3, Switch Bounced
The ISL1221 can operate independently or in conjunction
with a microcontroller for low power operation modes or in
battery backup modes.
The event detection and time stamp circuits operate in either
main VDD power or battery backup mode.
Users have the option to connect EVIN (see EVINEB bit) to
an internal pull-up current source that operates at 1µA
(always on mode), which can drop to 400nA in battery
backup mode. User selectable event sampling modes are
also available which will effectively reduce power
consumption with 1/4-Hz, 1-Hz and 2-Hz sample detection
rates. The EVIN input is pulsed ON/OFF when in sampling
mode for power savings advantages (See tables below).
The EVIN also has a user selectable time based hysteresis
filter (see EHYS bits) to implement switch de-bouncing
during an event detection. The EVIN signal must be high for
the duration of the selected time period. The time periods
available are 0 times delay (no time based hysteresis) to
3.9ms, 15.625ms or 31.25ms (see Table 1, 2, 3, and 4).
Real Time Clock Operation
The Real Time Clock (RTC) uses an external 32.768kHz
quartz crystal to maintain an accurate internal representation
of second, minute, hour, day of week, date, month, and year.
The RTC also has leap-year correction. The clock also
corrects for months having fewer than 31 days and has a bit
that controls 24 hour or AM/PM format. When the ISL1221
powers up after the loss of both VDD and VBAT, the clock will
not begin incrementing until at least one byte is written to the
clock register.
8 CLKS (8x)
15 CLKS (8x)
OFF
ON
OPEN
CLOSED
LOW
HIGH
HIGH
LOW
EVDET
EVIN
EXT.
SWITCH
Ipu
8 CLKS (8x)
15 CLKS (8x)
OFF
ON
OPEN
CLOSED
LOW
HIGH
HIGH
LOW
EVDET
EVIN
EXT.
SWITCH
Ipu
15 CLKS (8x)
OFF
ON
OPEN
CLOSED
LOW
HIGH
HIGH
LOW
EVDET
EVIN
EXT.
SWITCH
Ipu
8 CLKS (8x)
TABLE 1.
∆IDD (VDD = 3V, tHYS = 3.9ms)
fSMP
DELTA IDD
1/4Hz
20.5nA
1Hz
82nA
2Hz
164nA
TABLE 2.
∆IDD (VDD = 5.0V, tHYS = 3.9ms)
fSMP
DELTA IDD
1/4Hz
65.8nA
1Hz
263.3nA
2Hz
526.5nA
TABLE 3.
∆IDD (VDD = 3.0V, tHYS = 15.625ms)
fSMP
DELTA IDD
1/4Hz
82nA
1Hz
328nA
2Hz
656.3nA
TABLE 4.
∆IDD (VDD = 5.0V, tHYS = 15.625ms)
fSMP
DELTA IDD
1/4Hz
264nA
1Hz
1.05µA
2Hz
2.1µA
ISL1221


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