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ISL22426WFV14Z Arkusz danych(PDF) 2 Page - Intersil Corporation |
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ISL22426WFV14Z Arkusz danych(HTML) 2 Page - Intersil Corporation |
2 / 15 page 2 FN6180.2 September 8, 2009 Block Diagram VCC RH0 RH1 GND RL0 RL1 RW0 RW1 SCK SDI SDO CS WR1 WR0 SHDN POWER-UP INTERFACE, CONTROL AND STATUS LOGIC NON- VOLATILE REGISTERS SPI INTERFACE Pin Descriptions TSSOP PIN NUMBER QFN PIN NUMBER SYMBOL DESCRIPTION 115 VCC Power supply pin 216 SHDN Shutdown active low input 3 1 RH0 “High” terminal of DCP0 4 2 RL0 “Low” terminal of DCP0 5 3 RW0 “Wiper” terminal of DCP0 6 4, 5, 9 NC No connect 7 6 SCK SPI interface clock input 8 7 SDO Open drain SPI interface Data Output 9 8 GND Device ground pin 10 10 RW1 “Wiper” terminal of DCP1 11 11 RL1 “Low” terminal of DCP1 12 12 RH1 “High” terminal of DCP1 13 13 CS Chip Select active low input 14 14 SDI SPI interface Data Input EPAD* Exposed Die Pad internally connected to GND *NOTE: PCB thermal land for QFN EPAD should be connected to GND plane or left floating. For more information refer to http://www.intersil.com/data/tb/TB389.pdf ISL22426 |
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