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74LV4020N Arkusz danych(PDF) 11 Page - NXP Semiconductors |
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74LV4020N Arkusz danych(HTML) 11 Page - NXP Semiconductors |
11 / 20 page 74LV4020_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 29 November 2005 11 of 20 Philips Semiconductors 74LV4020 14-stage binary ripple counter [1] Typical values are measured at nominal VCC and Tamb = 25 °C. [2] CPD is used to determine the dynamic power dissipation (PD in µW). PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(C L × VCC 2 × f o) = sum of the outputs. tW pulse width CP (HIGH and LOW) see Figure 7 VCC = 2.0 V 41 - - ns VCC = 2.7 V 30 - - ns VCC = 3.0 V to 3.6 V 24 - - ns VCC = 4.5 V to 5.5 V 18 - - ns MR (HIGH) see Figure 8 VCC = 2.0 V 41 - - ns VCC = 2.7 V 30 - - ns VCC = 3.0 V to 3.6 V 24 - - ns VCC = 4.5 V to 5.5 V 18 - - ns trec recovery time MR to CP see Figure 8 VCC = 1.2 V ---ns VCC = 2.0 V 26 - - ns VCC = 2.7 V 19 - - ns VCC = 3.0 V to 3.6 V 15 - - ns VCC = 4.5 V to 5.5 V 12 - - ns fmax maximum input clock frequency see Figure 7 VCC = 2.0 V 12 - - MHz VCC = 2.7 V 16 - - MHz VCC = 3.0 V to 3.6 V 20 - - MHz VCC = 4.5 V to 5.5 V 30 - - MHz Table 8: Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF; for test circuit see Figure 9. Symbol Parameter Conditions Min Typ Max Unit |
Podobny numer części - 74LV4020N |
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Podobny opis - 74LV4020N |
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