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74LV4020D Arkusz danych(PDF) 2 Page - NXP Semiconductors

Numer części 74LV4020D
Szczegółowy opis  14-stage binary ripple counter
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74LV4020D Arkusz danych(HTML) 2 Page - NXP Semiconductors

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74LV4020_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 29 November 2005
2 of 20
Philips Semiconductors
74LV4020
14-stage binary ripple counter
4.
Quick reference data
[1]
CPD is used to determine the dynamic power dissipation (PD in µW).
PD =CPD × VCC2 × fi × N+ ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(C
L × VCC
2
× f
o) = sum of outputs.
5.
Ordering information
Table 1:
Quick reference data
GND = 0 V; Tamb =25 °C; tr =tf = 2.5 ns.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
tPHL,
tPLH
propagation delay
CL = 15 pF; VCC = 3.3 V
CP to Q0
-
12
-
ns
Qn to Q(n+1)
-
7
-
ns
tPHL
propagation delay
CL = 15 pF; VCC = 3.3 V
MR to Qn
-
16
-
ns
fmax
maximum input clock
frequency
CL = 15 pF; VCC = 3.3 V
-
100
-
MHz
Ci
input capacitance
-
3.5
-
pF
CPD
power dissipation
capacitance
per gate; VI = GND to
VCC
[1] -20
-
pF
Table 2:
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74LV4020N
−40 °C to +125 °C
DIP16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
74LV4020D
−40 °C to +125 °C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74LV4020DB
−40 °C to +125 °C
SSOP16
plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74LV4020PW
−40 °C to +125 °C
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1


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