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74LV4020D Arkusz danych(PDF) 1 Page - NXP Semiconductors |
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74LV4020D Arkusz danych(HTML) 1 Page - NXP Semiconductors |
1 / 20 page 1. General description The 74LV4020 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC4020 and 74HCT4020. The 74LV4020 is a 14-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and 12 fully buffered parallel outputs (Q0, and Q3 to Q13). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. 2. Features s Optimized for low-voltage applications: 1.0 V to 5.5 V s Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V s Typical LOW-level output voltage (peak) or output ground bounce: VOL(p) < 0.8 V at VCC = 3.3 V and Tamb =25 °C s Typical HIGH-level output voltage (valley) or output VOH undershoot: VOH(v) >2V at VCC = 3.3 V and Tamb =25 °C s ESD protection: x HBM EIA/JESD22-A114-C exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V. s Multiple package options s Specified from −40 °C to +80 °C and from −40 °C to +125 °C. 3. Applications s Frequency dividing circuits s Time delay circuits s Control counters 74LV4020 14-stage binary ripple counter Rev. 01 — 29 November 2005 Product data sheet |
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