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AD21462WBBZ3 Arkusz danych(PDF) 4 Page - Analog Devices |
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AD21462WBBZ3 Arkusz danych(HTML) 4 Page - Analog Devices |
4 / 60 page Rev. PrA | Page 4 of 60 | November 2008 ADSP-21462W/ADSP-21465W/ADSP-21467 Preliminary Technical Data GENERAL DESCRIPTION The ADSP-21462W/ADSP-21465W/ADSP-21467 SHARC® processors are members of the SIMD SHARC family of DSPs that feature Analog Devices' Super Harvard Architecture. The processors are source code compatible with the ADSP-2126x, ADSP-2136x, ADSP-2137x, and ADSP-2116x DSPs as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode. These new processors are 32-bit/40-bit floating point processors optimized for high performance audio applications with its large on-chip SRAM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital applications interface (DAI). As shown in the functional block diagram on Page 1, the processor uses two computational units to deliver a significant performance increase over the previous SHARC processors on a range of DSP algorithms. Fabricated in a state-of-the-art, high speed, CMOS process, the processor achieves an instruction cycle time of 2.22 ns at 450 MHz (ADSP-21467) and 2.5 ns at 400 MHz (ADSP-21462W, ADSP-21465W). With its SIMD computational hardware, the processors can perform 2.7 GFLOPS running at 450 MHz (ADSP-21467) and 2.4 GFLOPS running at 400 MHz (ADSP-21462W, ADSP-21465W). Table 2 shows performance benchmarks for the ADSP-2146x processors. Table 1. SHARC Family Features Feature Frequency 400 MHz 400 MHz 450 MHz RAM 5M bits 5M bits 5M bits ROM1 4M bits 4M bits 4M bits Audio Decoders in ROM No Yes Yes Pulse-Width Modulation Yes Yes Yes S/PDIF Yes Yes Yes DTCP2 Yes Yes No DDR2 Memory Interface 1/2 CCLK Max 1/2 CCLK Max 1/2 CCLK Max DDR2 Memory Bus Width 16 bits 16 bits 16 bits Direct DMA from SPORTs to external memory Yes Yes Yes FIR accelerator Yes Yes Yes IIR accelerator Yes Yes Yes FFT accelerator Yes Yes Yes MLB Interface Yes Yes No IDP Yes Yes Yes Serial Ports 8 8 8 SRU 2 2 2 DDR2 Memory Interface Yes Yes Yes UART 1 1 1 DAI and DPI 20/14 pins 20/14 pins 20/14 pins Link ports 2 2 2 S/PDIF transceiver 1 1 1 AMI interface with 8-bit support Yes Yes Yes SPI 2 2 2 TWI Yes Yes Yes Package 324-ball PBGA 324-ball PBGA 324-ball PBGA SRC Performance 128 dB 128 dB 128 dB 1 Audio decoding algorithms include PCM, Dolby Digital EX, Dolby Prologic IIx, DTS 96/24, Neo:6, DTS ES, MPEG-2 AAC, MP3, and functions like bass management, delay, speaker equalization, graphic equalization, and more. Decoder/post-processor algorithm combination support varies depending upon the chip version and the system configurations. Please visit www.analog.com for complete information. 2 The ADSP-21462W and ADSP-21465W processors provide the Digital Trans- mission Content Protection protocol, a proprietary security protocol. Contact your Analog Devices sales office for more information. Table 2. Processor Benchmarks Benchmark Algorithm Speed (at 450 MHz) 1024 Point Complex FFT (Radix 4, With Reversal) 20.44 μs FIR Filter (per Tap)1 1 Assumes two files in multichannel SIMD mode 1.11 ns IIR Filter (per Biquad)1 4.43 ns Matrix Multiply (Pipelined) [3 × 3] × [3 × 1] [4 × 4] × [4 × 1] 10.0 ns 17.78 ns Divide (y/×) 6.67 ns Inverse Square Root 10.0 ns Table 1. SHARC Family Features (Continued) Feature |
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