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ISL24201IRTZ Arkusz danych(PDF) 8 Page - Intersil Corporation

Numer części ISL24201IRTZ
Szczegółowy opis  Programmable VCOM Calibrator with EEPROM Pb-free (RoHS-compliant)
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Producent  INTERSIL [Intersil Corporation]
Strona internetowa  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL24201IRTZ Arkusz danych(HTML) 8 Page - Intersil Corporation

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ISL24201
8
FN7586.1
December 9, 2010
Table 1 shows the calculated results of the VCOM voltage with
these values.
Figure 6 is used to find the minimum saturation voltage for an
IOUT maximum of 100µA, which is about 0.3V. The minimum
VOUT is 6.5V, which also meets the minimum VOUT - VSET
requirements specified in Equation 14:
OUT Pin Leakage Current
When the voltage on the OUT pin is greater than 10V, there is a
leakage current flowing into the pin in addition to the ISET
current. Figure 9 shows the ISET current and the OUT pin current
for OUT pin voltage up to 19V. In applications where the voltage
on the OUT pin will be greater than 10V, the actual output voltage
will be lower than the voltage calculated by Equation 6. The
graph in Figure 9 was measured with RSET = 4.99kΩ.
Power Supply Sequence
The recommended power supply sequencing is shown in
Figure 10. When applying power, VDD should be applied before or
at the same time as AVDD. The minimum time for tVS is 0µs.
When removing power, the sequence of VDD and AVDD is not
important.
Do not remove VDD or AVDD within 100ms of the start of the
EEPROM programming cycle. Removing power before the
EEPROM programming cycle is completed may result in
corrupted data in the EEPROM.
Operating and Programming
Supply Voltage and Current
To program the EEPROM, AVDD must be ≥10.8V. If programming
is not required, the ISL24201 will operate over an AVDD range of
4.5V to 19V.
During EEPROM programming, IDD and IAVDD will temporarily be
higher than their quiescent currents. Figure 11 shows a typical
IDD and IAVDD current profile during EEPROM programming. The
current pulses are Erase and Write cycles. The EEPROM
programming algorithm is shown in Figure 12. The algorithm
allows up to 4 erase cycles and 4 programming cycles, however
typical parts only require 1 cycle of each, sometimes 2 when
AVDD is near the minimum 10.8V limit.
TABLE 1. EXAMPLE VOUT vs REGISTER VALUE
REGISTER VALUE
VOUT (V)
08.49
20
8.34
40
8.18
60
8.02
80
7.87
100
7.71
120
7.55
127
7.50
140
7.40
160
7.24
180
7.09
200
6.93
220
6.77
240
6.62
255
6.50
VOUTMIN
6.5V
15V
20
----------
>
0.3V
+
1.05V
==
(EQ. 14)
0.000
0.050
0.100
0.150
0.200
0.250
0.300
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
20.0
OUT PinVoltage(V)
OUT and SET Pin Current vs. OUT Pin Voltage
Register = 255
OUT Pin Current
SET Pin Current
FIGURE 9. OUT PIN LEAKAGE CURRENT
VDD
AVDD
tVS
FIGURE 10. POWER SUPPLY SEQUENCE


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