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LC4101C Arkusz danych(PDF) 4 Page - Sanyo Semicon Device |
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LC4101C Arkusz danych(HTML) 4 Page - Sanyo Semicon Device |
4 / 9 page Switching Characteristics at VDD = 5 V ± 10%, Ta = –20 to +75°C at VDD = 3 to 4.5 V, Ta = –20 to +75°C Note: 1. Since this IC detects the EIO inputs on the rising edge of the CP signal, the EIO inputs must be set up before the first data is input. As a result, a tho(ld) clock stop period is required directly after the rise of the LOAD signal if the clock frequency is relatively high. Note: 2. If this IC is used with a 4-bit width data input, the number of data clocks between one LOAD and the next LOAD must be doubled. No. 5280-4/9 LC4101C Parameter Symbol Conditions min typ max Unit EIO output delay time td (eo) 30 pF capacitive load 39 ns LD/EIO output delay time td (leo) 30 pF capacitive load 70 ns LOAD-OUTn delay time td (ldo) 100 pF capacitive load 700 µs DF-OUTn delay time td (dfo) 100 pF capacitive load 1.4 µs Parameter Symbol Conditions min typ max Unit EIO output delay time td (eo) 30 pF capacitive load 80 ns LD/EIO output delay time td (leo) 30 pF capacitive load 130 ns LOAD-OUTn delay time td (ldo) 100 pF capacitive load 3 µs DF-OUTn delay time td (dfo) 100 pF capacitive load 3 µs |
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